main.tan.summary

采用Verilog HDL语言编写的步进电机位置系统

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.500 ns
From           : Step_Sum[3]
To             : sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23]
From Clock     : 
To Clock       : Reset
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 24.700 ns
From           : sum_control:inst5|out_control
To             : Pulse_Wave
From Clock     : Clock_8MHz
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.800 ns
From           : Reset
To             : Pulse_Wave
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 16.600 ns
From           : Reset
To             : sum_control:inst5|out_control
From Clock     : 
To Clock       : Clock_8MHz
Failed Paths   : 0

Type           : Clock Setup: 'Clock_8MHz'
Slack          : N/A
Required Time  : None
Actual Time    : 62.50 MHz ( period = 16.000 ns )
From           : sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
To             : sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16]
From Clock     : Clock_8MHz
To Clock       : Clock_8MHz
Failed Paths   : 0

Type           : Clock Setup: 'Reset'
Slack          : N/A
Required Time  : None
Actual Time    : 87.72 MHz ( period = 11.400 ns )
From           : sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
To             : sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16]
From Clock     : Reset
To Clock       : Reset
Failed Paths   : 0

Type           : Clock Hold: 'Clock_8MHz'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22]
To             : sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23]
From Clock     : Clock_8MHz
To Clock       : Clock_8MHz
Failed Paths   : 601

Type           : Clock Hold: 'Reset'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22]
To             : sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23]
From Clock     : Reset
To Clock       : Reset
Failed Paths   : 376

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 977

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