main.tan.rpt

采用Verilog HDL语言编写的步进电机位置系统

; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                             ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+------------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From                                                                                  ; To                                                                                    ; From Clock ; To Clock   ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+------------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 10.500 ns                        ; Step_Sum[3]                                                                           ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ;            ; Reset      ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 24.700 ns                        ; sum_control:inst5|out_control                                                         ; Pulse_Wave                                                                            ; Clock_8MHz ;            ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 10.800 ns                        ; Reset                                                                                 ; Pulse_Wave                                                                            ;            ;            ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 16.600 ns                        ; Reset                                                                                 ; sum_control:inst5|out_control                                                         ;            ; Clock_8MHz ; 0            ;
; Clock Setup: 'Clock_8MHz'    ; N/A                                      ; None          ; 62.50 MHz ( period = 16.000 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Clock_8MHz ; Clock_8MHz ; 0            ;
; Clock Setup: 'Reset'         ; N/A                                      ; None          ; 87.72 MHz ( period = 11.400 ns ) ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[16] ; Reset      ; Reset      ; 0            ;
; Clock Hold: 'Clock_8MHz'     ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Clock_8MHz ; Clock_8MHz ; 601          ;
; Clock Hold: 'Reset'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[22] ; sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter|q[23] ; Reset      ; Reset      ; 376          ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                                       ;                                                                                       ;            ;            ; 977          ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------+------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K10TC100-1      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Reset           ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; Clock_8MHz      ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;