📄 pulse_sum.tan.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 20 19:51:50 2006 " "Info: Processing started: Thu Jul 20 19:51:50 2006" { } { } 0} } { } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off pulse_sum -c pulse_sum " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off pulse_sum -c pulse_sum" { } { } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[0\]~510 " "Info: Node \"pulse_1\[0\]~510\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[1\]~506 " "Info: Node \"pulse_1\[1\]~506\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[2\]~502 " "Info: Node \"pulse_1\[2\]~502\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[3\]~498 " "Info: Node \"pulse_1\[3\]~498\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[4\]~494 " "Info: Node \"pulse_1\[4\]~494\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[5\]~490 " "Info: Node \"pulse_1\[5\]~490\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[6\]~486 " "Info: Node \"pulse_1\[6\]~486\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[7\]~482 " "Info: Node \"pulse_1\[7\]~482\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[8\]~478 " "Info: Node \"pulse_1\[8\]~478\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[9\]~474 " "Info: Node \"pulse_1\[9\]~474\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[10\]~470 " "Info: Node \"pulse_1\[10\]~470\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[11\]~466 " "Info: Node \"pulse_1\[11\]~466\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[12\]~462 " "Info: Node \"pulse_1\[12\]~462\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[13\]~458 " "Info: Node \"pulse_1\[13\]~458\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[14\]~454 " "Info: Node \"pulse_1\[14\]~454\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_1\[15\]~450 " "Info: Node \"pulse_1\[15\]~450\"" { } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Reset pulse_out 9.900 ns Longest " "Info: Longest tpd from source pin \"Reset\" to destination pin \"pulse_out\" is 9.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Reset 1 PIN PIN_85 49 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_85; Fanout = 49; PIN Node = 'Reset'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" Compiler "pulse_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/" "" "" { Reset } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.800 ns) 5.000 ns pulse_1\[15\]~450 2 COMB LOOP LC17 3 " "Info: 2: + IC(0.000 ns) + CELL(4.800 ns) = 5.000 ns; Loc. = LC17; Fanout = 3; COMB LOOP Node = 'pulse_1\[15\]~450'" { { "Info" "ITDB_PART_OF_SCC" "pulse_1\[15\]~450 LC17 " "Info: Loc. = LC17; Node \"pulse_1\[15\]~450\"" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" Compiler "pulse_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/" "" "" { pulse_1[15]~450 } "NODE_NAME" } "" } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" Compiler "pulse_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/" "" "" { pulse_1[15]~450 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" Compiler "pulse_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/" "" "4.800 ns" { Reset pulse_1[15]~450 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(3.500 ns) 9.700 ns pulse_out~25 3 COMB LC33 1 " "Info: 3: + IC(1.200 ns) + CELL(3.500 ns) = 9.700 ns; Loc. = LC33; Fanout = 1; COMB Node = 'pulse_out~25'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" Compiler "pulse_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/" "" "4.700 ns" { pulse_1[15]~450 pulse_out~25 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 9.900 ns pulse_out 4 PIN PIN_40 0 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 9.900 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'pulse_out'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" Compiler "pulse_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/" "" "0.200 ns" { pulse_out~25 pulse_out } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/pulse_sum.v" 9 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.700 ns 87.88 % " "Info: Total cell delay = 8.700 ns ( 87.88 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 12.12 % " "Info: Total interconnect delay = 1.200 ns ( 12.12 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum_cmp.qrpt" Compiler "pulse_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/db/pulse_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_sum/" "" "9.900 ns" { Reset pulse_1[15]~450 pulse_out~25 pulse_out } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "9.900 ns" { Reset Reset~out pulse_1[15]~450 pulse_out~25 pulse_out } { 0.000ns 0.000ns 0.000ns 1.200ns 0.000ns } { 0.000ns 0.200ns 4.800ns 3.500ns 0.200ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 20 19:51:52 2006 " "Info: Processing ended: Thu Jul 20 19:51:52 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0} } { } 0}
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