📄 second_pulse_latch.fit.rpt
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; lpm_add_sub:add_rtl_0|addcore:adder[1]|g4~17 ; 4 ;
; lpm_add_sub:add_rtl_1|addcore:adder[1]|g4~17 ; 4 ;
; lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~70 ; 3 ;
; lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[1]~69 ; 3 ;
+-----------------------------------------------------------------------------------+---------+
+-------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+--------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+--------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 155 / 288 ( 53 % ) ;
; PIAs ; 182 / 288 ( 63 % ) ;
+----------------------------+--------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 22.75) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 1 ;
; 12 - 14 ; 1 ;
; 15 - 17 ; 0 ;
; 18 - 20 ; 0 ;
; 21 - 23 ; 1 ;
; 24 - 26 ; 2 ;
; 27 - 29 ; 2 ;
; 30 - 32 ; 1 ;
+-----------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------+
; LAB Macrocells ;
+-----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 11.63) ; Number of LABs (Total = 8) ;
+-----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
; 16 ; 3 ;
+-----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 15 ;
; 2 ; 4 ;
; 3 ; 1 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 9.63) ; Number of LABs (Total = 8) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 3 ;
; 12 ; 1 ;
; 13 ; 2 ;
+-------------------------------------------------+-----------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC3 ; Clk_1Hz, Reset, acceleration[16], lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~17, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~17 ; lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~15, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~16, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~24, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~29, lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~42, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~56, lpm_add_sub:add_rtl_1|addcore:adder[0]|p2c[2]~27, lpm_add_sub:add_rtl_1|addcore:adder[0]|p2c[2]~34, second_pulse_out[3], lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~30, lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~43, lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~57, lpm_add_sub:add_rtl_0|addcore:adder[0]|bg_out~39, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~89, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~92, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~95, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~96 ;
; A ; LC8 ; Clk_1Hz, Reset, acceleration[16], lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~30, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~29 ; lpm_add_sub:add_rtl_1|addcore:adder[0]|g2cp[2]~23, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~27, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~28, lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~30, lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39, lpm_add_sub:add_rtl_1|addcore:adder[0]|p2c[2]~34, lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~28, second_pulse_out[4], lpm_add_sub:add_rtl_0|addcore:adder[0]|bg_out~39, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~84, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~86, lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~80, lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~82, lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~42, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~98 ;
; A ; LC6 ; Clk_1Hz, Reset, second_pulse_out~1202 ; lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~17, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~25, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~29, lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~42, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~56, lpm_add_sub:add_rtl_1|addcore:adder[0]|p2c[2]~28, lpm_add_sub:add_rtl_1|addcore:adder[0]|p2c[2]~34, second_pulse_out~1202, second_pulse_out[2], lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~17, lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~27, lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~30, lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~40, lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~43, lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~57, lpm_add_sub:add_rtl_0|addcore:adder[0]|bg_out~39, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~80, second_pulse_out~1262, second_pulse_out~1267, lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~76, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~90, lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~93 ;
; A ; LC2 ; lpm_add_sub:add_rtl_1|addcore:adder[1]|g4~17, lpm_add_sub:add_rtl_1|addcore:adder[0]|genr_node[3]~88, lpm_add_sub:add_rtl_1|addcore:adder[0]|prop_node[3]~77, lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39, lpm_add_sub:add_rtl_1|addcore:adder[1]|g2cp[2]~23, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[7]~58, lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[7]~59, lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[7]~58, lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[6]~50, lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[5]~41, lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[4]~33, lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~67, lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[2]~16bal, lpm_add_sub:add_rtl_1|addcore:adder[1]|ps[0]~29sexpbal ; second_pulse_out[15]~reg0 ⌨️ 快捷键说明
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