second_pulse_latch.tan.qmsg

采用Verilog HDL语言编写的步进电机位置系统

{ "Info" "ITDB_TH_RESULT" "second_pulse_out\[7\]~reg0 acceleration\[7\] Clk_1Hz -0.800 ns register " "Info: th for register \"second_pulse_out\[7\]~reg0\" (data pin = \"acceleration\[7\]\", clock pin = \"Clk_1Hz\") is -0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_1Hz destination 2.200 ns + Longest register " "Info: + Longest clock path from clock \"Clk_1Hz\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns Clk_1Hz 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'Clk_1Hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "" { Clk_1Hz } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns second_pulse_out\[7\]~reg0 2 REG LC75 42 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC75; Fanout = 42; REG Node = 'second_pulse_out\[7\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "0.600 ns" { Clk_1Hz second_pulse_out[7]~reg0 } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "2.200 ns" { Clk_1Hz second_pulse_out[7]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clk_1Hz Clk_1Hz~out second_pulse_out[7]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns acceleration\[7\] 1 PIN PIN_51 41 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_51; Fanout = 41; PIN Node = 'acceleration\[7\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "" { acceleration[7] } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.000 ns) 4.700 ns second_pulse_out\[7\]~reg0 2 REG LC75 42 " "Info: 2: + IC(1.500 ns) + CELL(3.000 ns) = 4.700 ns; Loc. = LC75; Fanout = 42; REG Node = 'second_pulse_out\[7\]~reg0'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "4.500 ns" { acceleration[7] second_pulse_out[7]~reg0 } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns 68.09 % " "Info: Total cell delay = 3.200 ns ( 68.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 31.91 % " "Info: Total interconnect delay = 1.500 ns ( 31.91 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "4.700 ns" { acceleration[7] second_pulse_out[7]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { acceleration[7] acceleration[7]~out second_pulse_out[7]~reg0 } { 0.000ns 0.000ns 1.500ns } { 0.000ns 0.200ns 3.000ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "2.200 ns" { Clk_1Hz second_pulse_out[7]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clk_1Hz Clk_1Hz~out second_pulse_out[7]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "4.700 ns" { acceleration[7] second_pulse_out[7]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.700 ns" { acceleration[7] acceleration[7]~out second_pulse_out[7]~reg0 } { 0.000ns 0.000ns 1.500ns } { 0.000ns 0.200ns 3.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 19 23:02:21 2006 " "Info: Processing ended: Wed Jul 19 23:02:21 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}