📄 second_pulse_latch.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk_1Hz register second_pulse_out\[5\]~reg0 register second_pulse_out\[15\]~reg0 45.87 MHz 21.8 ns Internal " "Info: Clock \"Clk_1Hz\" has Internal fmax of 45.87 MHz between source register \"second_pulse_out\[5\]~reg0\" and destination register \"second_pulse_out\[15\]~reg0\" (period= 21.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.400 ns + Longest register register " "Info: + Longest register to register delay is 19.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns second_pulse_out\[5\]~reg0 1 REG LC40 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC40; Fanout = 19; REG Node = 'second_pulse_out\[5\]~reg0'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "" { second_pulse_out[5]~reg0 } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(3.700 ns) 5.400 ns lpm_add_sub:add_rtl_1\|addcore:adder\[0\]\|bg_out~29 2 COMB SEXP38 10 " "Info: 2: + IC(1.700 ns) + CELL(3.700 ns) = 5.400 ns; Loc. = SEXP38; Fanout = 10; COMB Node = 'lpm_add_sub:add_rtl_1\|addcore:adder\[0\]\|bg_out~29'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "5.400 ns" { second_pulse_out[5]~reg0 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~29 } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/addcore.tdf" 644 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 9.400 ns lpm_add_sub:add_rtl_1\|addcore:adder\[0\]\|bg_out~39 3 COMB LC34 11 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 9.400 ns; Loc. = LC34; Fanout = 11; COMB Node = 'lpm_add_sub:add_rtl_1\|addcore:adder\[0\]\|bg_out~39'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "4.000 ns" { lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~29 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39 } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/addcore.tdf" 644 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(4.000 ns) 15.000 ns lpm_add_sub:add_rtl_1\|addcore:adder\[1\]\|a_csnbuffer:result_node\|sout_node\[7\]~60 4 COMB LC2 1 " "Info: 4: + IC(1.600 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = LC2; Fanout = 1; COMB Node = 'lpm_add_sub:add_rtl_1\|addcore:adder\[1\]\|a_csnbuffer:result_node\|sout_node\[7\]~60'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "5.600 ns" { lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39 lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[7]~60 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 42 13 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.000 ns) 19.400 ns second_pulse_out\[15\]~reg0 5 REG LC57 5 " "Info: 5: + IC(1.400 ns) + CELL(3.000 ns) = 19.400 ns; Loc. = LC57; Fanout = 5; REG Node = 'second_pulse_out\[15\]~reg0'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "4.400 ns" { lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[7]~60 second_pulse_out[15]~reg0 } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.700 ns 75.77 % " "Info: Total cell delay = 14.700 ns ( 75.77 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.700 ns 24.23 % " "Info: Total interconnect delay = 4.700 ns ( 24.23 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "19.400 ns" { second_pulse_out[5]~reg0 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~29 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39 lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[7]~60 second_pulse_out[15]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "19.400 ns" { second_pulse_out[5]~reg0 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~29 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39 lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[7]~60 second_pulse_out[15]~reg0 } { 0.000ns 1.700ns 0.000ns 1.600ns 1.400ns } { 0.000ns 3.700ns 4.000ns 4.000ns 3.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_1Hz destination 2.200 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk_1Hz\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns Clk_1Hz 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'Clk_1Hz'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "" { Clk_1Hz } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns second_pulse_out\[15\]~reg0 2 REG LC57 5 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC57; Fanout = 5; REG Node = 'second_pulse_out\[15\]~reg0'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "0.600 ns" { Clk_1Hz second_pulse_out[15]~reg0 } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "2.200 ns" { Clk_1Hz second_pulse_out[15]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clk_1Hz Clk_1Hz~out second_pulse_out[15]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_1Hz source 2.200 ns - Longest register " "Info: - Longest clock path from clock \"Clk_1Hz\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns Clk_1Hz 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'Clk_1Hz'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "" { Clk_1Hz } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns second_pulse_out\[5\]~reg0 2 REG LC40 19 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC40; Fanout = 19; REG Node = 'second_pulse_out\[5\]~reg0'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "0.600 ns" { Clk_1Hz second_pulse_out[5]~reg0 } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "2.200 ns" { Clk_1Hz second_pulse_out[5]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clk_1Hz Clk_1Hz~out second_pulse_out[5]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "2.200 ns" { Clk_1Hz second_pulse_out[15]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clk_1Hz Clk_1Hz~out second_pulse_out[15]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "2.200 ns" { Clk_1Hz second_pulse_out[5]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clk_1Hz Clk_1Hz~out second_pulse_out[5]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "19.400 ns" { second_pulse_out[5]~reg0 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~29 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39 lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[7]~60 second_pulse_out[15]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "19.400 ns" { second_pulse_out[5]~reg0 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~29 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39 lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[7]~60 second_pulse_out[15]~reg0 } { 0.000ns 1.700ns 0.000ns 1.600ns 1.400ns } { 0.000ns 3.700ns 4.000ns 4.000ns 3.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "2.200 ns" { Clk_1Hz second_pulse_out[15]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clk_1Hz Clk_1Hz~out second_pulse_out[15]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "2.200 ns" { Clk_1Hz second_pulse_out[5]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clk_1Hz Clk_1Hz~out second_pulse_out[5]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "second_pulse_out\[14\]~reg0 acceleration\[5\] Clk_1Hz 18.400 ns register " "Info: tsu for register \"second_pulse_out\[14\]~reg0\" (data pin = \"acceleration\[5\]\", clock pin = \"Clk_1Hz\") is 18.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.600 ns + Longest pin register " "Info: + Longest pin to register delay is 19.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns acceleration\[5\] 1 PIN PIN_16 18 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_16; Fanout = 18; PIN Node = 'acceleration\[5\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "" { acceleration[5] } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(3.700 ns) 5.600 ns lpm_add_sub:add_rtl_1\|addcore:adder\[0\]\|bg_out~29 2 COMB SEXP38 10 " "Info: 2: + IC(1.700 ns) + CELL(3.700 ns) = 5.600 ns; Loc. = SEXP38; Fanout = 10; COMB Node = 'lpm_add_sub:add_rtl_1\|addcore:adder\[0\]\|bg_out~29'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "5.400 ns" { acceleration[5] lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~29 } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/addcore.tdf" 644 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 9.600 ns lpm_add_sub:add_rtl_1\|addcore:adder\[0\]\|bg_out~39 3 COMB LC34 11 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 9.600 ns; Loc. = LC34; Fanout = 11; COMB Node = 'lpm_add_sub:add_rtl_1\|addcore:adder\[0\]\|bg_out~39'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "4.000 ns" { lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~29 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39 } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/addcore.tdf" 644 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(4.000 ns) 15.200 ns lpm_add_sub:add_rtl_1\|addcore:adder\[1\]\|a_csnbuffer:result_node\|sout_node\[6\]~51 4 COMB LC12 1 " "Info: 4: + IC(1.600 ns) + CELL(4.000 ns) = 15.200 ns; Loc. = LC12; Fanout = 1; COMB Node = 'lpm_add_sub:add_rtl_1\|addcore:adder\[1\]\|a_csnbuffer:result_node\|sout_node\[6\]~51'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "5.600 ns" { lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39 lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[6]~51 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 42 13 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.000 ns) 19.600 ns second_pulse_out\[14\]~reg0 5 REG LC53 14 " "Info: 5: + IC(1.400 ns) + CELL(3.000 ns) = 19.600 ns; Loc. = LC53; Fanout = 14; REG Node = 'second_pulse_out\[14\]~reg0'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "4.400 ns" { lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[6]~51 second_pulse_out[14]~reg0 } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.900 ns 76.02 % " "Info: Total cell delay = 14.900 ns ( 76.02 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.700 ns 23.98 % " "Info: Total interconnect delay = 4.700 ns ( 23.98 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "19.600 ns" { acceleration[5] lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~29 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39 lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[6]~51 second_pulse_out[14]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "19.600 ns" { acceleration[5] acceleration[5]~out lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~29 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39 lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[6]~51 second_pulse_out[14]~reg0 } { 0.000ns 0.000ns 1.700ns 0.000ns 1.600ns 1.400ns } { 0.000ns 0.200ns 3.700ns 4.000ns 4.000ns 3.000ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_1Hz destination 2.200 ns - Shortest register " "Info: - Shortest clock path from clock \"Clk_1Hz\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns Clk_1Hz 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'Clk_1Hz'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "" { Clk_1Hz } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns second_pulse_out\[14\]~reg0 2 REG LC53 14 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC53; Fanout = 14; REG Node = 'second_pulse_out\[14\]~reg0'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "0.600 ns" { Clk_1Hz second_pulse_out[14]~reg0 } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "2.200 ns" { Clk_1Hz second_pulse_out[14]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clk_1Hz Clk_1Hz~out second_pulse_out[14]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "19.600 ns" { acceleration[5] lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~29 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39 lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[6]~51 second_pulse_out[14]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "19.600 ns" { acceleration[5] acceleration[5]~out lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~29 lpm_add_sub:add_rtl_1|addcore:adder[0]|bg_out~39 lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node|sout_node[6]~51 second_pulse_out[14]~reg0 } { 0.000ns 0.000ns 1.700ns 0.000ns 1.600ns 1.400ns } { 0.000ns 0.200ns 3.700ns 4.000ns 4.000ns 3.000ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "2.200 ns" { Clk_1Hz second_pulse_out[14]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clk_1Hz Clk_1Hz~out second_pulse_out[14]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk_1Hz second_pulse_out\[15\] second_pulse_out\[15\]~reg0 4.000 ns register " "Info: tco from clock \"Clk_1Hz\" to destination pin \"second_pulse_out\[15\]\" through register \"second_pulse_out\[15\]~reg0\" is 4.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_1Hz source 2.200 ns + Longest register " "Info: + Longest clock path from clock \"Clk_1Hz\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns Clk_1Hz 1 CLK PIN_83 16 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_83; Fanout = 16; CLK Node = 'Clk_1Hz'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "" { Clk_1Hz } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.200 ns second_pulse_out\[15\]~reg0 2 REG LC57 5 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC57; Fanout = 5; REG Node = 'second_pulse_out\[15\]~reg0'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "0.600 ns" { Clk_1Hz second_pulse_out[15]~reg0 } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "2.200 ns" { Clk_1Hz second_pulse_out[15]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clk_1Hz Clk_1Hz~out second_pulse_out[15]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" { } { { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.400 ns + Longest register pin " "Info: + Longest register to pin delay is 0.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns second_pulse_out\[15\]~reg0 1 REG LC57 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC57; Fanout = 5; REG Node = 'second_pulse_out\[15\]~reg0'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "" { second_pulse_out[15]~reg0 } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 49 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 0.400 ns second_pulse_out\[15\] 2 PIN PIN_36 0 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 0.400 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'second_pulse_out\[15\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "0.400 ns" { second_pulse_out[15]~reg0 second_pulse_out[15] } "NODE_NAME" } "" } } { "second_pulse_latch.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v" 9 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns 100.00 % " "Info: Total cell delay = 0.400 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "0.400 ns" { second_pulse_out[15]~reg0 second_pulse_out[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.400 ns" { second_pulse_out[15]~reg0 second_pulse_out[15] } { 0.000ns 0.000ns } { 0.000ns 0.400ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "2.200 ns" { Clk_1Hz second_pulse_out[15]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clk_1Hz Clk_1Hz~out second_pulse_out[15]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.600ns 0.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch_cmp.qrpt" Compiler "second_pulse_latch" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/db/second_pulse_latch.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/" "" "0.400 ns" { second_pulse_out[15]~reg0 second_pulse_out[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.400 ns" { second_pulse_out[15]~reg0 second_pulse_out[15] } { 0.000ns 0.000ns } { 0.000ns 0.400ns } } } } 0}
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