second_pulse_latch.fit.eqn

采用Verilog HDL语言编写的步进电机位置系统

A1L85_p2_out = !acceleration[16] & !A1L92Q & !acceleration[0] & A1L13Q;
A1L85_p3_out = !acceleration[0] & A1L13Q & !acceleration[1];
A1L85_p4_out = !acceleration[16] & !A1L92Q & A1L13Q & !A1L72Q;
A1L85_or_out = A1L16 # A1L85_p0_out # A1L85_p2_out # A1L85_p3_out # A1L85_p4_out;
A1L85 = acceleration[2] $ A1L85_or_out;


--A1L13Q is second_pulse_out[2]~reg0 at LC6
A1L13Q_p1_out = !Reset & A1L85;
A1L13Q_or_out = A1L13Q_p1_out;
A1L13Q_reg_input = A1L13Q_or_out;
A1L13Q = DFFE(A1L13Q_reg_input, GLOBAL(Clk_1Hz), , , );


--F3L1 is lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[4]~17 at LC48
F3L1_p1_out = C6L21 & F21L31;
F3L1_p0_out = !A1L72Q & acceleration[1] & acceleration[0] & !A1L13Q;
F3L1_p2_out = acceleration[2] & !A1L72Q & acceleration[1] & acceleration[0];
F3L1_p3_out = !A1L72Q & acceleration[0] & !A1L92Q & !A1L13Q;
F3L1_p4_out = acceleration[1] & !A1L92Q & !A1L13Q;
F3L1_or_out = F3L2 # F3L1_p0_out # F3L1_p2_out # F3L1_p3_out # F3L1_p4_out;
F3L1 = F3L1_p1_out $ F3L1_or_out;


--A1L33Q is second_pulse_out[3]~reg0 at LC3
A1L33Q_p1_out = !Reset & acceleration[16] & F3L1;
A1L33Q_p2_out = !Reset & !acceleration[16] & !F21L3;
A1L33Q_or_out = A1L33Q_p1_out # A1L33Q_p2_out;
A1L33Q_reg_input = A1L33Q_or_out;
A1L33Q = DFFE(A1L33Q_reg_input, GLOBAL(Clk_1Hz), , , );


--F3L3 is lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~24 at SEXP92
F3L3 = EXP(acceleration[1] & !A1L72Q & acceleration[0]);


--F3L4 is lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~26 at SEXP93
F3L4 = EXP(!A1L72Q & acceleration[0]);


--F3L5 is lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~27 at SEXP94
F3L5 = EXP(acceleration[2] & !A1L13Q);


--F3L6 is lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~28 at SEXP95
F3L6 = EXP(A1L53Q & acceleration[4]);


--F3L7 is lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[5]~30 at LC91
F3L7_p1_out = F3L6 & C6L5;
F3L7_p0_out = F21L5 & F3L5 & F3L4 & !acceleration[1];
F3L7_p2_out = A1L33Q & !acceleration[3];
F3L7_p3_out = F21L5 & !acceleration[2] & A1L13Q;
F3L7_p4_out = F21L5 & F3L5 & F3L3 & A1L92Q;
F3L7_or_out = F3L7_p0_out # F3L7_p2_out # F3L7_p3_out # F3L7_p4_out;
F3L7 = F3L7_p1_out $ F3L7_or_out;


--A1L53Q is second_pulse_out[4]~reg0 at LC8
A1L53Q_p1_out = !Reset & acceleration[16] & !F3L7;
A1L53Q_p2_out = !Reset & !acceleration[16] & !F21L21;
A1L53Q_or_out = A1L53Q_p1_out # A1L53Q_p2_out;
A1L53Q_reg_input = A1L53Q_or_out;
A1L53Q = DFFE(A1L53Q_reg_input, GLOBAL(Clk_1Hz), , , );


--F3L8 is lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~39 at SEXP55
F3L8 = EXP(A1L92Q & !acceleration[1]);


--F3L9 is lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~40 at SEXP58
F3L9 = EXP(!acceleration[2] & A1L13Q);


--F3L01 is lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~41 at SEXP59
F3L01 = EXP(A1L73Q & acceleration[5]);


--F3L11 is lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~43 at LC50
F3L11_p1_out = F3L01 & C6L6;
F3L11_p0_out = F21L01 & F21L6 & F3L9 & F3L8 & !A1L72Q & acceleration[0];
F3L11_p2_out = F21L01 & !A1L33Q & acceleration[3];
F3L11_p3_out = F21L01 & F21L6 & acceleration[2] & !A1L13Q;
F3L11_p4_out = F21L01 & F21L6 & F3L9 & !A1L92Q & acceleration[1];
F3L11_or_out = F3L21 # F3L11_p0_out # F3L11_p2_out # F3L11_p3_out # F3L11_p4_out;
F3L11 = F3L11_p1_out $ F3L11_or_out;


--A1L73Q is second_pulse_out[5]~reg0 at LC40
A1L73Q_p1_out = !Reset & acceleration[16] & F3L11;
A1L73Q_p2_out = !Reset & !acceleration[16] & !F21L22;
A1L73Q_or_out = A1L73Q_p1_out # A1L73Q_p2_out;
A1L73Q_reg_input = A1L73Q_or_out;
A1L73Q = DFFE(A1L73Q_reg_input, GLOBAL(Clk_1Hz), , , );


--F3L31 is lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~55 at SEXP60
F3L31 = EXP(!A1L93Q & !acceleration[6]);


--F3L41 is lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~56 at SEXP62
F3L41 = EXP(acceleration[6] & A1L93Q);


--F3L51 is lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node|sout_node[7]~57 at LC52
F3L51_p1_out = F3L31 & F3L41;
F3L51_p0_out = F21L42 & F21L01 & F21L6 & F3L9 & F3L8 & !A1L72Q & acceleration[0];
F3L51_p2_out = F21L42 & F21L01 & !A1L33Q & acceleration[3];
F3L51_p3_out = F21L42 & F21L01 & F21L6 & acceleration[2] & !A1L13Q;
F3L51_p4_out = F21L42 & F21L01 & F21L6 & F3L9 & !A1L92Q & acceleration[1];
F3L51_or_out = F3L61 # F3L51_p0_out # F3L51_p2_out # F3L51_p3_out # F3L51_p4_out;
F3L51 = F3L51_p1_out $ F3L51_or_out;


--A1L93Q is second_pulse_out[6]~reg0 at LC56
A1L93Q_p1_out = !Reset & acceleration[16] & F3L51;
A1L93Q_p2_out = !Reset & !acceleration[16] & !F21L72;
A1L93Q_or_out = A1L93Q_p1_out # A1L93Q_p2_out;
A1L93Q_reg_input = A1L93Q_or_out;
A1L93Q = DFFE(A1L93Q_reg_input, GLOBAL(Clk_1Hz), , , );


--C2L2 is lpm_add_sub:add_rtl_0|addcore:adder[0]|genr_node[3]~82 at LC25
C2L2_p1_out = A1L93Q & !acceleration[6];
C2L2_p2_out = A1L93Q & A1L73Q & !acceleration[5];
C2L2_p3_out = !acceleration[6] & A1L73Q & !acceleration[5];
C2L2_or_out = C2L2_p1_out # C2L2_p2_out # C2L2_p3_out;
C2L2 = C2L2_or_out;


--C2L1 is lpm_add_sub:add_rtl_0|addcore:adder[0]|bg_out~39 at LC89
C2L1_p0_out = F21L91 & F21L5 & F3L5 & F3L4 & !acceleration[1];
C2L1_p1_out = A1L53Q & !acceleration[4];
C2L1_p2_out = F21L91 & A1L33Q & !acceleration[3];
C2L1_p3_out = F21L91 & F21L5 & A1L13Q & !acceleration[2];
C2L1_p4_out = F21L91 & F21L5 & F3L5 & F3L3 & A1L92Q;
C2L1_or_out = C2L1_p0_out # C2L1_p1_out # C2L1_p2_out # C2L1_p3_out # C2L1_p4_out;
C2L1 = C2L1_or_out;


--A1L14Q is second_pulse_out[7]~reg0 at LC75
A1L14Q_p0_out = !Reset & !acceleration[16] & !acceleration[7] & !A1L14Q & !C6L41;
A1L14Q_p1_out = !C6L7 & !Reset & !acceleration[16] & !acceleration[7] & A1L14Q & C6L41;
A1L14Q_p2_out = C6L7 & !Reset & !acceleration[16] & acceleration[7] & A1L14Q;
A1L14Q_p3_out = !Reset & !acceleration[16] & acceleration[7] & A1L14Q & !C6L41;
A1L14Q_p4_out = C6L7 & !Reset & !acceleration[16] & !acceleration[7] & !A1L14Q;
A1L14Q_or_out = A1L36 # A1L14Q_p0_out # A1L14Q_p1_out # A1L14Q_p2_out # A1L14Q_p3_out # A1L14Q_p4_out;
A1L14Q_reg_input = A1L14Q_or_out;
A1L14Q = DFFE(A1L14Q_reg_input, GLOBAL(Clk_1Hz), , , );


--C3L41 is lpm_add_sub:add_rtl_0|addcore:adder[1]|prop_node[0]~105 at LC22
C3L41_p1_out = A1L14Q & A1L34Q;
C3L41_p2_out = A1L14Q & !acceleration[8];
C3L41_p3_out = A1L34Q & !acceleration[7];
C3L41_p4_out = !acceleration[8] & !acceleration[7];
C3L41_or_out = C3L41_p1_out # C3L41_p2_out # C3L41_p3_out # C3L41_p4_out;
C3L41 = C3L41_or_out;


--A1L34Q is second_pulse_out[8]~reg0 at LC69
A1L34Q_p0_out = !Reset & !acceleration[16] & C6L3 & !A1L34Q & !acceleration[8] & C6L61;
A1L34Q_p1_out = !C6L9 & !Reset & !acceleration[16] & !C6L3 & A1L34Q & !acceleration[8];
A1L34Q_p2_out = C6L9 & !Reset & !acceleration[16] & A1L34Q & acceleration[8];
A1L34Q_p3_out = C6L9 & !Reset & !acceleration[16] & !A1L34Q & !acceleration[8];
A1L34Q_p4_out = !Reset & !acceleration[16] & C6L3 & A1L34Q & acceleration[8] & C6L61;
A1L34Q_or_out = A1L66 # A1L34Q_p0_out # A1L34Q_p1_out # A1L34Q_p2_out # A1L34Q_p3_out # A1L34Q_p4_out;
A1L34Q_reg_input = A1L34Q_or_out;
A1L34Q = DFFE(A1L34Q_reg_input, GLOBAL(Clk_1Hz), , , );


--C3L01 is lpm_add_sub:add_rtl_0|addcore:adder[1]|genr_node[0]~91 at LC32
C3L01_p1_out = A1L34Q & !acceleration[8];
C3L01_p2_out = A1L34Q & A1L14Q & !acceleration[7];
C3L01_p3_out = !acceleration[8] & A1L14Q & !acceleration[7];
C3L01_or_out = C3L01_p1_out # C3L01_p2_out # C3L01_p3_out;
C3L01 = C3L01_or_out;


--F6L1 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[2]~15 at SEXP79
F6L1 = EXP(A1L54Q & acceleration[9]);


--F6L3 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[2]~17 at LC65
F6L3_p1_out = F6L1 & F6L2;
F6L3_p0_out = A1L34Q & !acceleration[8];
F6L3_p2_out = C2L2 & C3L91 & C3L81;
F6L3_p3_out = C2L3 & C2L1 & C3L91 & C3L81;
F6L3_p4_out = C3L91 & A1L14Q & !acceleration[7];
F6L3_or_out = F6L3_p0_out # F6L3_p2_out # F6L3_p3_out # F6L3_p4_out;
F6L3 = F6L3_p1_out $ F6L3_or_out;


--A1L54Q is second_pulse_out[9]~reg0 at LC37
A1L54Q_p1_out = !Reset & acceleration[16] & !F6L3;
A1L54Q_p2_out = !Reset & !acceleration[16] & !F51L3;
A1L54Q_or_out = A1L54Q_p1_out # A1L54Q_p2_out;
A1L54Q_reg_input = A1L54Q_or_out;
A1L54Q = DFFE(A1L54Q_reg_input, GLOBAL(Clk_1Hz), , , );


--C3L51 is lpm_add_sub:add_rtl_0|addcore:adder[1]|prop_node[1]~110 at LC16
C3L51_p1_out = A1L74Q & A1L54Q;
C3L51_p2_out = A1L74Q & !acceleration[9];
C3L51_p3_out = A1L54Q & !acceleration[10];
C3L51_p4_out = !acceleration[9] & !acceleration[10];
C3L51_or_out = C3L51_p1_out # C3L51_p2_out # C3L51_p3_out # C3L51_p4_out;
C3L51 = C3L51_or_out;


--C3L8 is lpm_add_sub:add_rtl_0|addcore:adder[1]|gcp[2]~12 at LC80
C3L8_p0_out = A1L14Q & !acceleration[7] & !acceleration[8] & !acceleration[9];
C3L8_p1_out = A1L54Q & A1L34Q & A1L14Q & !acceleration[7];
C3L8_p2_out = A1L54Q & A1L14Q & !acceleration[7] & !acceleration[8];
C3L8_p3_out = A1L34Q & !acceleration[8] & !acceleration[9];
C3L8_p4_out = A1L34Q & A1L14Q & !acceleration[7] & !acceleration[9];
C3L8_or_out = C3L9 # C3L8_p0_out # C3L8_p1_out # C3L8_p2_out # C3L8_p3_out # C3L8_p4_out;
C3L8 = C3L8_or_out;


--F6L4 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~24 at SEXP104
F6L4 = EXP(A1L74Q & acceleration[10]);


--F6L5 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~25 at SEXP107
F6L5 = EXP(!acceleration[10] & !A1L74Q);


--F6L6 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[3]~26 at LC103
F6L6_p1_out = F6L4 & F6L5;
F6L6_p2_out = C2L2 & C3L91 & C3L81 & F51L4;
F6L6_p3_out = C2L3 & C2L1 & C3L91 & C3L81 & F51L4;
F6L6_or_out = F6L6_p2_out # F6L6_p3_out # C3L8;
F6L6 = F6L6_p1_out $ F6L6_or_out;


--A1L74Q is second_pulse_out[10]~reg0 at LC45
A1L74Q_p1_out = !Reset & acceleration[16] & !F6L6;
A1L74Q_p2_out = !Reset & !acceleration[16] & !F51L8;
A1L74Q_or_out = A1L74Q_p1_out # A1L74Q_p2_out;
A1L74Q_reg_input = A1L74Q_or_out;
A1L74Q = DFFE(A1L74Q_reg_input, GLOBAL(Clk_1Hz), , , );


--C3L5 is lpm_add_sub:add_rtl_0|addcore:adder[1]|g4~17 at LC72
C3L5_p1_out = !acceleration[10] & A1L74Q;
C3L5_p0_out = !acceleration[10] & !A1L74Q & !acceleration[8] & A1L14Q & !acceleration[7] & !acceleration[9];
C3L5_p2_out = A1L54Q & !acceleration[10] & !A1L74Q & !acceleration[8] & A1L14Q & !acceleration[7];
C3L5_p3_out = !acceleration[10] & !A1L74Q & !acceleration[8] & A1L34Q & !acceleration[9];
C3L5_p4_out = !acceleration[10] & !A1L74Q & A1L14Q & !acceleration[7] & A1L34Q & !acceleration[9];
C3L5_or_out = C3L7 # C3L5_p0_out # C3L5_p2_out # C3L5_p3_out # C3L5_p4_out;
C3L5 = C3L5_p1_out $ C3L5_or_out;


--C3L11 is lpm_add_sub:add_rtl_0|addcore:adder[1]|genr_node[1]~95 at LC14
C3L11_p1_out = A1L74Q & !acceleration[10];
C3L11_p2_out = A1L74Q & A1L54Q & !acceleration[9];
C3L11_p3_out = !acceleration[10] & A1L54Q & !acceleration[9];
C3L11_or_out = C3L11_p1_out # C3L11_p2_out # C3L11_p3_out;
C3L11 = C3L11_or_out;


--F6L8 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[4]~32 at SEXP110
F6L8 = EXP(A1L94Q & acceleration[11]);


--F6L9 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[4]~33 at SEXP5
F6L9 = EXP(!acceleration[11] & !A1L94Q);


--F6L01 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[4]~34 at LC101
F6L01_p1_out = F6L8 & F6L11;
F6L01_p2_out = C2L2 & F51L7 & C3L91 & C3L81 & F51L4;
F6L01_p3_out = C2L3 & C2L1 & F51L7 & C3L91 & C3L81 & F51L4;
F6L01_or_out = F6L01_p2_out # F6L01_p3_out # C3L5;
F6L01 = F6L01_p1_out $ F6L01_or_out;


--A1L94Q is second_pulse_out[11]~reg0 at LC46
A1L94Q_p1_out = !Reset & acceleration[16] & !F6L01;
A1L94Q_p2_out = !Reset & !acceleration[16] & !F51L21;
A1L94Q_or_out = A1L94Q_p1_out # A1L94Q_p2_out;
A1L94Q_reg_input = A1L94Q_or_out;
A1L94Q = DFFE(A1L94Q_reg_input, GLOBAL(Clk_1Hz), , , );


--F6L21 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[5]~40 at SEXP29
F6L21 = EXP(A1L15Q & acceleration[12]);


--F6L31 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[5]~41 at SEXP6
F6L31 = EXP(!acceleration[12] & !A1L15Q);


--F6L41 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[5]~42 at LC31
F6L41_p1_out = F6L21 & F6L51;
F6L41_p0_out = A1L94Q & !acceleration[11];
F6L41_p2_out = C3L5 & F51L31;
F6L41_p3_out = C2L2 & F51L9 & C3L91 & C3L81 & F51L5 & F51L31;
F6L41_p4_out = C2L3 & C2L1 & F51L9 & C3L91 & C3L81 & F51L5 & F51L31;
F6L41_or_out = F6L41_p0_out # F6L41_p2_out # F6L41_p3_out # F6L41_p4_out;
F6L41 = F6L41_p1_out $ F6L41_or_out;


--A1L15Q is second_pulse_out[12]~reg0 at LC64
A1L15Q_p1_out = !Reset & acceleration[16] & !F6L41;
A1L15Q_p2_out = !Reset & !acceleration[16] & !F51L61;
A1L15Q_or_out = A1L15Q_p1_out # A1L15Q_p2_out;
A1L15Q_reg_input = A1L15Q_or_out;
A1L15Q = DFFE(A1L15Q_reg_input, GLOBAL(Clk_1Hz), , , );


--C3L61 is lpm_add_sub:add_rtl_0|addcore:adder[1]|prop_node[2]~115 at LC10
C3L61_p1_out = A1L15Q & A1L94Q;
C3L61_p2_out = A1L15Q & !acceleration[11];
C3L61_p3_out = A1L94Q & !acceleration[12];
C3L61_p4_out = !acceleration[11] & !acceleration[12];
C3L61_or_out = C3L61_p1_out # C3L61_p2_out # C3L61_p3_out # C3L61_p4_out;
C3L61 = C3L61_or_out;


--C3L21 is lpm_add_sub:add_rtl_0|addcore:adder[1]|genr_node[2]~99 at LC9
C3L21_p1_out = A1L15Q & !acceleration[12];
C3L21_p2_out = A1L15Q & A1L94Q & !acceleration[11];
C3L21_p3_out = !acceleration[12] & A1L94Q & !acceleration[11];
C3L21_or_out = C3L21_p1_out # C3L21_p2_out # C3L21_p3_out;
C3L21 = C3L21_or_out;


--C3L2 is lpm_add_sub:add_rtl_0|addcore:adder[1]|g2cp[1]~17 at LC5
C3L2_p1_out = A1L15Q & !acceleration[12];
C3L2_p2_out = A1L15Q & A1L94Q & !acceleration[11];
C3L2_p3_out = !acceleration[12] & A1L94Q & !acceleration[11];
C3L2_or_out = C3L2_p1_out # C3L2_p2_out # C3L2_p3_out;
C3L2 = C3L2_or_out;


--F6L61 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[6]~49 at SEXP30
F6L61 = EXP(A1L35Q & acceleration[13]);


--F6L71 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[6]~50 at SEXP8
F6L71 = EXP(!acceleration[13] & !A1L35Q);


--F6L81 is lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node|sout_node[6]~51 at LC28
F6L81_p1_out = F6L61 & F6L91;
F6L81_p2_out = C3L5 & F51L31 & F51L71;
F6L81_p3_out = C2L2 & F51L9 & C3L91 & C3L81 & F51L5 & F51L31 & F51L71;
F6L81_p4_out = C2L3 & C2L1 & F51L9 & C3L91 & C3L81 & F51L5 & F51L31 & F51L71;
F6L81_or_out = C3L2 # F6L81_p2_out # F6L81_p3_out # F6L81_p4_out;