second_pulse_latch.map.rpt

采用Verilog HDL语言编写的步进电机位置系统

           |-- a_csnbuffer:oflow_node
           |-- a_csnbuffer:result_node
      |-- altshift:carry_ext_latency_ffs
      |-- look_add:look_ahead_unit
      |-- altshift:oflow_ext_latency_ffs
      |-- altshift:result_ext_latency_ffs


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                         ;
+------------------------------------+------------+------+------------------------------------------------------------------------------------+
; Compilation Hierarchy Node         ; Macrocells ; Pins ; Full Hierarchy Name                                                                ;
+------------------------------------+------------+------+------------------------------------------------------------------------------------+
; |second_pulse_latch                ; 93         ; 51   ; |second_pulse_latch                                                                ;
;    |lpm_add_sub:add_rtl_0|         ; 37         ; 0    ; |second_pulse_latch|lpm_add_sub:add_rtl_0                                          ;
;       |addcore:adder[0]|           ; 10         ; 0    ; |second_pulse_latch|lpm_add_sub:add_rtl_0|addcore:adder[0]                         ;
;          |a_csnbuffer:result_node| ; 7          ; 0    ; |second_pulse_latch|lpm_add_sub:add_rtl_0|addcore:adder[0]|a_csnbuffer:result_node ;
;       |addcore:adder[1]|           ; 25         ; 0    ; |second_pulse_latch|lpm_add_sub:add_rtl_0|addcore:adder[1]                         ;
;          |a_csnbuffer:result_node| ; 7          ; 0    ; |second_pulse_latch|lpm_add_sub:add_rtl_0|addcore:adder[1]|a_csnbuffer:result_node ;
;       |addcore:adder[2]|           ; 2          ; 0    ; |second_pulse_latch|lpm_add_sub:add_rtl_0|addcore:adder[2]                         ;
;          |a_csnbuffer:result_node| ; 2          ; 0    ; |second_pulse_latch|lpm_add_sub:add_rtl_0|addcore:adder[2]|a_csnbuffer:result_node ;
;    |lpm_add_sub:add_rtl_1|         ; 31         ; 0    ; |second_pulse_latch|lpm_add_sub:add_rtl_1                                          ;
;       |addcore:adder[0]|           ; 15         ; 0    ; |second_pulse_latch|lpm_add_sub:add_rtl_1|addcore:adder[0]                         ;
;          |a_csnbuffer:result_node| ; 7          ; 0    ; |second_pulse_latch|lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node ;
;       |addcore:adder[1]|           ; 16         ; 0    ; |second_pulse_latch|lpm_add_sub:add_rtl_1|addcore:adder[1]                         ;
;          |a_csnbuffer:result_node| ; 7          ; 0    ; |second_pulse_latch|lpm_add_sub:add_rtl_1|addcore:adder[1]|a_csnbuffer:result_node ;
+------------------------------------+------------+------+------------------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.map.eqn.


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                  ;
+----------------------------------+-----------------+------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                                       ;
+----------------------------------+-----------------+------------------------------------------------------------------------------------+
; second_pulse_latch.v             ; yes             ; E:/戴仙金/资料/Verilog书/源代码/step_motor/second_pulse_latch/second_pulse_latch.v ;
; lpm_add_sub.tdf                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf                        ;
; addcore.inc                      ; yes             ; d:/altera/quartus42/libraries/megafunctions/addcore.inc                            ;
; look_add.inc                     ; yes             ; d:/altera/quartus42/libraries/megafunctions/look_add.inc                           ;
; bypassff.inc                     ; yes             ; d:/altera/quartus42/libraries/megafunctions/bypassff.inc                           ;
; altshift.inc                     ; yes             ; d:/altera/quartus42/libraries/megafunctions/altshift.inc                           ;
; alt_stratix_add_sub.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_stratix_add_sub.inc                ;
; alt_mercury_add_sub.inc          ; yes             ; d:/altera/quartus42/libraries/megafunctions/alt_mercury_add_sub.inc                ;
; aglobal42.inc                    ; yes             ; d:/altera/quartus42/libraries/megafunctions/aglobal42.inc                          ;
; addcore.tdf                      ; yes             ; d:/altera/quartus42/libraries/megafunctions/addcore.tdf                            ;
; a_csnbuffer.inc                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.inc                        ;
; a_csnbuffer.tdf                  ; yes             ; d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf                        ;
; look_add.tdf                     ; yes             ; d:/altera/quartus42/libraries/megafunctions/look_add.tdf                           ;
; altshift.tdf                     ; yes             ; d:/altera/quartus42/libraries/megafunctions/altshift.tdf                           ;
+----------------------------------+-----------------+------------------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 93                   ;
; Total registers      ; 16                   ;
; I/O pins             ; 51                   ;
; Shareable expanders  ; 52                   ;
; Parallel expanders   ; 26                   ;
; Maximum fan-out node ; acceleration[16]     ;
; Maximum fan-out      ; 23                   ;
; Total fan-out        ; 796                  ;
; Average fan-out      ; 4.06                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Wed Jul 19 23:01:36 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off second_pulse_latch -c second_pulse_latch
Info: Found 1 design units, including 1 entities, in source file second_pulse_latch.v
    Info: Found entity 1: second_pulse_latch
Warning: Verilog HDL unsupported feature warning at second_pulse_latch.v(21): Initial Construct is not supported and will be ignored
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 32 buffer(s)
    Info: Ignored 32 SOFT buffer(s)
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "Clk_1Hz" to global clock signal
Warning: Design contains 16 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "speed[15]"
    Warning: No output dependent on input pin "speed[14]"
    Warning: No output dependent on input pin "speed[13]"
    Warning: No output dependent on input pin "speed[12]"
    Warning: No output dependent on input pin "speed[11]"
    Warning: No output dependent on input pin "speed[10]"
    Warning: No output dependent on input pin "speed[9]"
    Warning: No output dependent on input pin "speed[8]"
    Warning: No output dependent on input pin "speed[7]"
    Warning: No output dependent on input pin "speed[6]"
    Warning: No output dependent on input pin "speed[5]"
    Warning: No output dependent on input pin "speed[4]"
    Warning: No output dependent on input pin "speed[3]"
    Warning: No output dependent on input pin "speed[2]"
    Warning: No output dependent on input pin "speed[1]"
    Warning: No output dependent on input pin "speed[0]"
Info: Implemented 196 device resources after synthesis - the final resource count might be different
    Info: Implemented 35 input pins
    Info: Implemented 16 output pins
    Info: Implemented 93 macrocells
    Info: Implemented 52 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings
    Info: Processing ended: Wed Jul 19 23:02:05 2006
    Info: Elapsed time: 00:00:30