second_pulse_latch.tan.summary

采用Verilog HDL语言编写的步进电机位置系统

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 18.400 ns
From           : acceleration[0]
To             : second_pulse_out[15]~reg0
From Clock     : 
To Clock       : Clk_1Hz
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 4.000 ns
From           : second_pulse_out[0]~reg0
To             : second_pulse_out[0]
From Clock     : Clk_1Hz
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.800 ns
From           : acceleration[7]
To             : second_pulse_out[7]~reg0
From Clock     : 
To Clock       : Clk_1Hz
Failed Paths   : 0

Type           : Clock Setup: 'Clk_1Hz'
Slack          : N/A
Required Time  : None
Actual Time    : 45.87 MHz ( period = 21.800 ns )
From           : second_pulse_out[1]~reg0
To             : second_pulse_out[14]~reg0
From Clock     : Clk_1Hz
To Clock       : Clk_1Hz
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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