fdiv.tan.rpt

采用Verilog HDL语言编写的步进电机位置系统

; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:CNT_rtl_0|dffs[1] ; lpm_counter:CNT_rtl_0|dffs[2] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:CNT_rtl_0|dffs[0] ; lpm_counter:CNT_rtl_0|dffs[0] ; Clock_8MHz ; Clock_8MHz ; None                        ; None                      ; 3.600 ns                ;
+-------+----------------------------------+-------------------------------+-------------------------------+------------+------------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------------------+
; tsu                                                                                    ;
+-------+--------------+------------+-------+-------------------------------+------------+
; Slack ; Required tsu ; Actual tsu ; From  ; To                            ; To Clock   ;
+-------+--------------+------------+-------+-------------------------------+------------+
; N/A   ; None         ; 3.300 ns   ; Reset ; lpm_counter:CNT_rtl_0|dffs[0] ; Clock_8MHz ;
; N/A   ; None         ; 3.300 ns   ; Reset ; lpm_counter:CNT_rtl_0|dffs[2] ; Clock_8MHz ;
; N/A   ; None         ; 3.300 ns   ; Reset ; lpm_counter:CNT_rtl_0|dffs[1] ; Clock_8MHz ;
; N/A   ; None         ; 3.300 ns   ; Reset ; lpm_counter:CNT_rtl_0|dffs[3] ; Clock_8MHz ;
+-------+--------------+------------+-------+-------------------------------+------------+


+--------------------------------------------------------------------------------------------+
; tco                                                                                        ;
+-------+--------------+------------+-------------------------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From                          ; To        ; From Clock ;
+-------+--------------+------------+-------------------------------+-----------+------------+
; N/A   ; None         ; 2.800 ns   ; lpm_counter:CNT_rtl_0|dffs[1] ; F_65536Hz ; Clock_8MHz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:CNT_rtl_0|dffs[3] ; F_1Hz     ; Clock_8MHz ;
+-------+--------------+------------+-------------------------------+-----------+------------+


+----------------------------------------------------------------------------------------------+
; th                                                                                           ;
+---------------+-------------+-----------+-------+-------------------------------+------------+
; Minimum Slack ; Required th ; Actual th ; From  ; To                            ; To Clock   ;
+---------------+-------------+-----------+-------+-------------------------------+------------+
; N/A           ; None        ; -0.800 ns ; Reset ; lpm_counter:CNT_rtl_0|dffs[0] ; Clock_8MHz ;
; N/A           ; None        ; -0.800 ns ; Reset ; lpm_counter:CNT_rtl_0|dffs[2] ; Clock_8MHz ;
; N/A           ; None        ; -0.800 ns ; Reset ; lpm_counter:CNT_rtl_0|dffs[1] ; Clock_8MHz ;
; N/A           ; None        ; -0.800 ns ; Reset ; lpm_counter:CNT_rtl_0|dffs[3] ; Clock_8MHz ;
+---------------+-------------+-----------+-------+-------------------------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Wed Jul 19 20:31:02 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off fdiv -c fdiv
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Clock_8MHz" is an undefined clock
Info: Clock "Clock_8MHz" has Internal fmax of 175.44 MHz between source register "lpm_counter:CNT_rtl_0|dffs[0]" and destination register "lpm_counter:CNT_rtl_0|dffs[3]" (period= 5.7 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0|dffs[0]'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC1; Fanout = 3; REG Node = 'lpm_counter:CNT_rtl_0|dffs[3]'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "Clock_8MHz" to destination register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'Clock_8MHz'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 3; REG Node = 'lpm_counter:CNT_rtl_0|dffs[3]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
        Info: - Longest clock path from clock "Clock_8MHz" to source register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'Clock_8MHz'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC3; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0|dffs[0]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: tsu for register "lpm_counter:CNT_rtl_0|dffs[0]" (data pin = "Reset", clock pin = "Clock_8MHz") is 3.300 ns
    Info: + Longest pin to register delay is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 7; PIN Node = 'Reset'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC3; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0|dffs[0]'
        Info: Total cell delay = 2.800 ns ( 73.68 % )
        Info: Total interconnect delay = 1.000 ns ( 26.32 % )
    Info: + Micro setup delay of destination is 0.800 ns
    Info: - Shortest clock path from clock "Clock_8MHz" to destination register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'Clock_8MHz'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC3; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0|dffs[0]'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: tco from clock "Clock_8MHz" to destination pin "F_65536Hz" through register "lpm_counter:CNT_rtl_0|dffs[1]" is 2.800 ns
    Info: + Longest clock path from clock "Clock_8MHz" to source register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'Clock_8MHz'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC2; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0|dffs[1]'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0|dffs[1]'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'F_65536Hz'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: th for register "lpm_counter:CNT_rtl_0|dffs[0]" (data pin = "Reset", clock pin = "Clock_8MHz") is -0.800 ns
    Info: + Longest clock path from clock "Clock_8MHz" to destination register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'Clock_8MHz'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC3; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0|dffs[0]'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.700 ns
    Info: - Shortest pin to register delay is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 7; PIN Node = 'Reset'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC3; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0|dffs[0]'
        Info: Total cell delay = 2.800 ns ( 73.68 % )
        Info: Total interconnect delay = 1.000 ns ( 26.32 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jul 19 20:31:03 2006
    Info: Elapsed time: 00:00:02