fdiv.tan.qmsg

采用Verilog HDL语言编写的步进电机位置系统

{ "Info" "ITDB_FULL_TCO_RESULT" "Clock_8MHz F_65536Hz lpm_counter:CNT_rtl_0\|dffs\[1\] 2.800 ns register " "Info: tco from clock \"Clock_8MHz\" to destination pin \"F_65536Hz\" through register \"lpm_counter:CNT_rtl_0\|dffs\[1\]\" is 2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_8MHz source 1.300 ns + Longest register " "Info: + Longest clock path from clock \"Clock_8MHz\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns Clock_8MHz 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'Clock_8MHz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "" { Clock_8MHz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/fdiv.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:CNT_rtl_0\|dffs\[1\] 2 REG LC2 5 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC2; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "0.100 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "1.300 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_8MHz Clock_8MHz~out lpm_counter:CNT_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:CNT_rtl_0\|dffs\[1\] 1 REG LC2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0\|dffs\[1\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "" { lpm_counter:CNT_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns F_65536Hz 2 PIN PIN_5 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'F_65536Hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "0.200 ns" { lpm_counter:CNT_rtl_0|dffs[1] F_65536Hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/fdiv.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns 100.00 % " "Info: Total cell delay = 0.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "0.200 ns" { lpm_counter:CNT_rtl_0|dffs[1] F_65536Hz } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { lpm_counter:CNT_rtl_0|dffs[1] F_65536Hz } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "1.300 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_8MHz Clock_8MHz~out lpm_counter:CNT_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "0.200 ns" { lpm_counter:CNT_rtl_0|dffs[1] F_65536Hz } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { lpm_counter:CNT_rtl_0|dffs[1] F_65536Hz } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter:CNT_rtl_0\|dffs\[0\] Reset Clock_8MHz -0.800 ns register " "Info: th for register \"lpm_counter:CNT_rtl_0\|dffs\[0\]\" (data pin = \"Reset\", clock pin = \"Clock_8MHz\") is -0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_8MHz destination 1.300 ns + Longest register " "Info: + Longest clock path from clock \"Clock_8MHz\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns Clock_8MHz 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'Clock_8MHz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "" { Clock_8MHz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/fdiv.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:CNT_rtl_0\|dffs\[0\] 2 REG LC3 5 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC3; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "0.100 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "1.300 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_8MHz Clock_8MHz~out lpm_counter:CNT_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Reset 1 PIN PIN_24 7 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 7; PIN Node = 'Reset'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "" { Reset } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/fdiv.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.800 ns lpm_counter:CNT_rtl_0\|dffs\[0\] 2 REG LC3 5 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC3; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "3.600 ns" { Reset lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 73.68 % " "Info: Total cell delay = 2.800 ns ( 73.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 26.32 % " "Info: Total interconnect delay = 1.000 ns ( 26.32 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "3.800 ns" { Reset lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { Reset Reset~out lpm_counter:CNT_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "1.300 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_8MHz Clock_8MHz~out lpm_counter:CNT_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/fdiv/" "" "3.800 ns" { Reset lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { Reset Reset~out lpm_counter:CNT_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 19 20:31:03 2006 " "Info: Processing ended: Wed Jul 19 20:31:03 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}