main.fit.summary

采用Verilog HDL语言编写的数字频率计

Flow Status : Successful - Mon Jul 17 23:30:09 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : main
Top-level Entity Name : main
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 251 / 256 ( 98 % )
Total pins : 24 / 164 ( 14 % )
Device : EPM7256SQC208-7
Timing Models : Final