dispselect.fit.eqn

采用Verilog HDL语言编写的数字频率计

--A1L12Q is disp_select[0]~reg0 at LC11
A1L12Q_p1_out = A1L32Q & A1L52Q & !A1L12Q;
A1L12Q_or_out = A1L12Q_p1_out;
A1L12Q_reg_input = !A1L12Q_or_out;
A1L12Q = TFFE(A1L12Q_reg_input, GLOBAL(clk), , , );


--A1L32Q is disp_select[1]~reg0 at LC10
A1L32Q_p1_out = !A1L52Q & A1L32Q & !A1L12Q;
A1L32Q_p2_out = !A1L52Q & !A1L32Q & A1L12Q;
A1L32Q_or_out = A1L32Q_p1_out # A1L32Q_p2_out;
A1L32Q_reg_input = A1L32Q_or_out;
A1L32Q = DFFE(A1L32Q_reg_input, GLOBAL(clk), , , );


--A1L52Q is disp_select[2]~reg0 at LC8
A1L52Q_p1_out = !A1L32Q & !A1L52Q;
A1L52Q_p2_out = !A1L52Q & !A1L12Q;
A1L52Q_p3_out = !A1L32Q & !A1L12Q;
A1L52Q_or_out = A1L52Q_p1_out # A1L52Q_p2_out # A1L52Q_p3_out;
A1L52Q_reg_input = !A1L52Q_or_out;
A1L52Q = TFFE(A1L52Q_reg_input, GLOBAL(clk), , , );


--A1L31Q is Q[5]~reg0 at LC7
A1L31Q_p1_out = !A1L52Q & !A1L32Q & !A1L12Q;
A1L31Q_or_out = A1L31Q_p1_out;
A1L31Q_reg_input = A1L31Q_or_out;
A1L31Q = DFFE(A1L31Q_reg_input, GLOBAL(clk), , , );


--A1L11Q is Q[4]~reg0 at LC6
A1L11Q_p1_out = !A1L52Q & !A1L32Q & A1L12Q;
A1L11Q_or_out = A1L11Q_p1_out;
A1L11Q_reg_input = A1L11Q_or_out;
A1L11Q = DFFE(A1L11Q_reg_input, GLOBAL(clk), , , );


--A1L9Q is Q[3]~reg0 at LC5
A1L9Q_p1_out = !A1L52Q & A1L32Q & !A1L12Q;
A1L9Q_or_out = A1L9Q_p1_out;
A1L9Q_reg_input = A1L9Q_or_out;
A1L9Q = DFFE(A1L9Q_reg_input, GLOBAL(clk), , , );


--A1L7Q is Q[2]~reg0 at LC3
A1L7Q_p1_out = !A1L52Q & A1L32Q & A1L12Q;
A1L7Q_or_out = A1L7Q_p1_out;
A1L7Q_reg_input = A1L7Q_or_out;
A1L7Q = DFFE(A1L7Q_reg_input, GLOBAL(clk), , , );


--A1L5Q is Q[1]~reg0 at LC2
A1L5Q_p1_out = A1L52Q & !A1L32Q & !A1L12Q;
A1L5Q_or_out = A1L5Q_p1_out;
A1L5Q_reg_input = A1L5Q_or_out;
A1L5Q = DFFE(A1L5Q_reg_input, GLOBAL(clk), , , );


--A1L3Q is Q[0]~reg0 at LC1
A1L3Q_p1_out = A1L52Q & !A1L32Q & A1L12Q;
A1L3Q_or_out = A1L3Q_p1_out;
A1L3Q_reg_input = A1L3Q_or_out;
A1L3Q = DFFE(A1L3Q_reg_input, GLOBAL(clk), , , );


--clk is clk at PIN_43
--operation mode is input

clk = INPUT();


--disp_select[0] is disp_select[0] at PIN_16
--operation mode is output

disp_select[0] = OUTPUT(A1L12Q);


--disp_select[1] is disp_select[1] at PIN_14
--operation mode is output

disp_select[1] = OUTPUT(A1L32Q);


--disp_select[2] is disp_select[2] at PIN_12
--operation mode is output

disp_select[2] = OUTPUT(A1L52Q);


--Q[5] is Q[5] at PIN_11
--operation mode is output

Q[5] = OUTPUT(A1L31Q);


--Q[4] is Q[4] at PIN_9
--operation mode is output

Q[4] = OUTPUT(A1L11Q);


--Q[3] is Q[3] at PIN_8
--operation mode is output

Q[3] = OUTPUT(A1L9Q);


--Q[2] is Q[2] at PIN_6
--operation mode is output

Q[2] = OUTPUT(A1L7Q);


--Q[1] is Q[1] at PIN_5
--operation mode is output

Q[1] = OUTPUT(A1L5Q);


--Q[0] is Q[0] at PIN_4
--operation mode is output

Q[0] = OUTPUT(A1L3Q);