sig_reg.vhd

BIST 电路IP核的VHDL语言源代码

library IEEE;
use IEEE.std_logic_1164.all;

entity signature_register is
port (
  data_in  : std_ulogic;
  clock    : std_ulogic;
  reset    : std_ulogic;
  data_out : out std_ulogic_vector(9 downto 0)
);
end signature_register;

architecture RTL of signature_register is

  signal lfsr_reg : std_ulogic_vector(9 downto 0);
  
begin

  process (clock)
    variable lfsr_tap : std_ulogic;
  begin
    if clock'EVENT and clock='1' then
      if reset = '1' then
        lfsr_reg <= (others => '0');
      else
        lfsr_tap := lfsr_reg(6) xor lfsr_reg(9);
        lfsr_reg <= lfsr_reg(8 downto 0) & (lfsr_tap xor data_in);
      end if;
    end if;
  end process;
  
  data_out <= lfsr_reg;

end RTL;