scan.vhd

本人写的一个秒表

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity scan is
  port(clk3 : in std_logic;
	   data0,data1,data2,data3,data4,data5 : in std_logic_vector(3 downto 0);
	   dataout : out std_logic_vector(3 downto 0);
	   selectout : out std_logic_vector(5 downto 0));
end entity scan;

architecture behave3 of scan is
signal temp1 : std_logic_vector(2 downto 0);
signal temp2 : std_logic_vector(3 downto 0);
  begin
	process(clk3,data0,data1,data2,data3,data4,data5)
	begin
	if clk3'event and clk3='1' then
		if temp1 = 5 then temp1 <= (others=>'0');
		else temp1 <= temp1 + 1;
		end if;
	end if;
	end process;
	process(temp1,clk3,data0,data1,data2,data3,data4,data5)
	begin
	case temp1 is
		when "000" => temp2 <= data0;selectout <= "000001";
		when "001" => temp2 <= data1;selectout <= "000010";
		when "010" => temp2 <= data2;selectout <= "000100";
		when "011" => temp2 <= data3;selectout <= "001000";
		when "100" => temp2 <= data4;selectout <= "010000";
		when "101" => temp2 <= data5;selectout <= "100000";
		when others => null;
	end case;
	end process;
	dataout <= temp2;
end architecture behave3;