count6.vhd

来自「本人写的一个秒表」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count6 is
	port(clk2 : in std_logic;
		 clr2: in std_logic;
		 --en2 : in std_logic;
		 data2 : out std_logic_vector(3 downto 0);
		 carry2 : out std_logic);
end entity count6;

architecture behave2 of count6 is  
begin
	process(clr2,clk2)
	variable temp : std_logic_vector(3 downto 0);
	 begin
	 if clr2='1' then temp := "0000";
	 else
		if clk2'event and clk2='1' then 
		if temp = 5 then temp := "0000";	
		else temp := temp + 1;
	    end if;
		end if;
	end if;
	if temp < 5 then carry2 <= '0';
	else carry2 <= '1';
	end if;
	 data2<= temp;
   end process ;
end architecture behave2;