decoder7s.vhd

来自「本人写的一个秒表」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity decoder7s is
	port(bcd : in std_logic_vector(3 downto 0);
		 deci : out std_logic_vector(6 downto 0));
end entity;

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architecture display of decoder7s is----common cathode
	begin
	process(bcd)
	begin
	case bcd is
		when "0000" => deci<= "0111111";---0
		when "0001" => deci<= "0000110";---1
		when "0010" => deci<= "1011011";---2
		when "0011" => deci<= "1001111";---3
		when "0100" => deci<= "1100110";---4
		when "0101" => deci<= "1101101";---5
		when "0110" => deci<= "1111101";---6
		when "0111" => deci<= "0000111";---7
		when "1000" => deci<= "1111111";---8
		when "1001" => deci<= "1101111";---9
		when others => null;
	end case;
	end process;
end architecture;