count10.vhd

来自「本人写的一个秒表」· VHDL 代码 · 共 32 行

---10进制计数 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count10 is
	port(clk1 : in std_logic;
		 clr1 : in std_logic;
		 --en1 : in std_logic;
		 data1 : out std_logic_vector(3 downto 0);
		 carry1 : out std_logic );
end entity count10;

architecture behave1 of count10 is 
begin
	process(clr1,clk1)
	variable temp : std_logic_vector(3 downto 0); 
	 begin
	 if clr1='1' then temp := "0000";
	 elsif clk1'event and clk1='1' then 
			--if en1 = '1' then 
		if temp < 9 then temp := temp + 1 ;
		else temp := (others => '0');
	    end if;
	 else null;
	end if;
	if temp < 9 then carry1 <= '0';
	else carry1 <= '1';
	end if;
	 data1 <= temp;
   end process ;
end architecture behave1;