stopwatch.vhd

本人写的一个秒表

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity stopwatch is
	port(clk20m: in std_logic;
		 clk_scan: in std_logic;
		 start_stop :in std_logic;
		 clr : in std_logic;
		 com7 : out std_logic_vector(6 downto 0);
		 select6 : out std_logic_vector(5 downto 0));
end entity stopwatch;

--------------------------------------------------

architecture behave of stopwatch is
component any_even is
	generic (data_width : integer := 18 );
	port(input1 : in std_logic_vector(data_width-1 downto 0);
		 clk_in : in std_logic;
		 clk_out : out std_logic);
end component any_even;
component count10 is------count10
	port(clk1 : in std_logic;
		 clr1 : in std_logic;
		 --en1 : in std_logic;
		 data1 : out std_logic_vector(3 downto 0);
		 carry1 : out std_logic);
end component count10;
-------
component count6 is-------count6
	port(clk2 : in std_logic;
		 clr2: in std_logic;
		 --en2 : in std_logic;
		 data2 : out std_logic_vector(3 downto 0);
		 carry2 : out std_logic);
end component count6;
------
component decoder7s is----decoder7s
	port(bcd : in std_logic_vector(3 downto 0);
		 deci : out std_logic_vector(6 downto 0));
end component decoder7s;
------
component scan is-------scan
	port(clk3 : in std_logic;
	   data0,data1,data2,data3,data4,data5 : in std_logic_vector(3 downto 0);
	   dataout : out std_logic_vector(3 downto 0);
	   selectout : out std_logic_vector(5 downto 0));
end component scan;
signal clk_temp : std_logic;
signal clk : std_logic;
signal carry_temp1,carry_temp2,carry_temp3,carry_temp4,carry_temp5,carry_temp6 : std_logic;
signal pointlow,pointhigh : std_logic_vector(3 downto 0);
signal secondlow,secondhigh : std_logic_vector(3 downto 0);
signal minutelow,minutehigh : std_logic_vector(3 downto 0);
signal display_temp : std_logic_vector(3 downto 0);
  begin
U1: count10 port map(clk_temp,clr,pointlow,carry_temp1);--小数的低位
U2: count10 port map(carry_temp1,clr,pointhigh,carry_temp2);--小数的高位
U3: count10 port map(carry_temp2,clr,secondlow,carry_temp3);--秒的低位
U4: count6  port map(carry_temp3,clr,secondhigh,carry_temp4);--秒的高位
U5: count10 port map(carry_temp4,clr,minutelow,carry_temp5);---分的低位
U6: count6  port map(carry_temp5,clr,minutehigh,carry_temp6);--分的高位
U7: scan    port map(clk_scan,pointlow,pointhigh,secondlow,secondhigh,minutelow,minutehigh,display_temp,select6);--动态扫描
U8: decoder7s port map(display_temp,com7);
U9: any_even port map ("110000110101000000",clk20m,clk);
	process(clk,start_stop,clr)
	begin
	if clr = '1' then clk_temp <= '0';
	elsif start_stop = '1' then clk_temp <= clk;
	else clk_temp <= '0';
	end if ;
end process;
end architecture behave;