clock.tan.summary

来自「功能更加完善的基于vhdl的数字时钟设计 有秒表」· SUMMARY 代码 · 共 107 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.200 ns
From           : date
To             : time:U3|clkc6
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 24.700 ns
From           : time:U3|cnt24:u3|lpm_counter:s1_rtl_2|alt_counter_f10ke:wysi_counter|q[0]
To             : co5[0]
From Clock     : set
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 17.700 ns
From           : date
To             : co3[2]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.800 ns
From           : rst
To             : time:U3|dy:U4|c
From Clock     : --
To Clock       : set
Failed Paths   : 0

Type           : Clock Setup: 'set'
Slack          : N/A
Required Time  : None
Actual Time    : 67.57 MHz ( period = 14.800 ns )
From           : time:U3|dy:U4|s1[2]
To             : time:U3|dy:U4|c
From Clock     : set
To Clock       : set
Failed Paths   : 0

Type           : Clock Setup: 'date'
Slack          : N/A
Required Time  : None
Actual Time    : 77.52 MHz ( period = 12.900 ns )
From           : time:U3|dy:U4|s1[2]
To             : time:U3|dy:U4|c
From Clock     : date
To Clock       : date
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 77.52 MHz ( period = 12.900 ns )
From           : time:U3|dy:U4|s1[2]
To             : time:U3|dy:U4|c
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clo'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 200.00 MHz ( period = 5.000 ns )
From           : cnt[0]
To             : cnt[0]
From Clock     : clo
To Clock       : clo
Failed Paths   : 0

Type           : Clock Hold: 'set'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : time:U3|cnt24:u3|lpm_counter:s1_rtl_2|alt_counter_f10ke:wysi_counter|q[1]
To             : time:U3|cnt24:u3|lpm_counter:s1_rtl_2|alt_counter_f10ke:wysi_counter|q[2]
From Clock     : set
To Clock       : set
Failed Paths   : 99

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 99

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