cnt100.vhd

来自「功能更加完善的基于vhdl的数字时钟设计 有秒表」· VHDL 代码 · 共 37 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt100 IS
    PORT (ce,rst,clk : IN STD_LOGIC;
             ca : OUT STD_LOGIC;
             co1,co2 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END cnt100;
ARCHITECTURE wav OF cnt100 IS
     SIGNAL s1,s2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
     SIGNAL c : STD_LOGIC;
        BEGIN
            PROCESS (clk,rst,ce)
                BEGIN
                   IF rst = '1' THEN 
                      s1 <= "0000";
                      s2 <= "0000";
                   ELSIF RISING_EDGE(clk)  THEN
                       IF ce = '1'  THEN
                           IF (s1 = 9) AND (s2 = 9)  THEN  
                             s1 <= "0000";
                             s2 <= "0000";
                             c <= '1';
                           ELSIF (s1 = 9)  THEN
                              s1 <= "0000";
                              s2 <= s2 + 1;
                              c <='0';
                           ELSE s1 <= s1 + 1;
                                c <= '0';
                           END IF;         
                       END IF;
                   END IF;
            END PROCESS;
    co1 <= s1;
    co2 <= s2; 
    ca <= c;
END wav;