control_wrr.vhd

用VHDL语言实现的以09449为桥接芯片的PCI接口

--cws [e-mail]
--control_wrr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control_wrr is
generic(
				data_width:natural:=32;
				mem_address_width:natural:=8;
				mem_address_out_width:natural:=9;
				address_width:natural:=13;
				adr_width:natural:=13;
				rx_width:natural:=16;
				tx_width:natural:=16;
				dq_width:natural:=32								
);
port(
		CLK:in std_logic;
		RST:in std_logic;
		M:out std_logic_vector(1 downto 0);		
		TXD:out std_logic;
		RXD:in std_logic;

		PASSENB:out std_logic;
		RXDATA:in std_logic;
		RXCNTL:in std_logic;
		RXFLAG:in std_logic;
		RXREADY:in std_logic;
		RXERROR:in std_logic;
		RXCLK0:in std_logic;
		RXDSLIP:in std_logic;
--		REFCLK :out std_logic;
		RX     :in std_logic_vector(rx_width-1 downto 0);
		
		TXDATA:out std_logic;		
		TX    :out std_logic_vector(tx_width-1 downto 0);
--		TCLK  :out std_logic;
		
		NIRO_IN:out std_logic;
		ALE:out std_logic;		
		NSTROBE:out std_logic;
		BE:out std_logic_vector(3 downto 0);
		NSELECT:out std_logic;
		NRead:out std_logic;
		NWrite:out std_logic;
		RDY_IN:out std_logic;
		RDY_OUT:in std_logic;
		BLAST:  out std_logic;
		ADR:out std_logic_vector(ADR_width-1 downto 0);
		DQ:inout std_logic_vector(DQ_width-1 downto 0)		 
);
end control_wrr;
architecture str of control_wrr is 
component control
port(
			MEM_IN_DATA:out std_logic_vector(Data_width-1 downto 0);
			MEM_IN_ADDRESS:out std_logic_vector(MEM_ADDRESS_width-1 downto 0);
			MEM_WR:out std_logic;
			MEM_FULL:in std_logic;
			MEM_OUT_DATA:in std_logic_vector(Data_width-1 downto 0);
			MEM_OUT_ADDRESS:out std_logic_vector(MEM_ADDRESS_out_width-1 downto 0);
			MEM_RD:out std_logic;
			MEM_EMPTY:in std_logic;
			
			CLK:IN std_logic;
			DATA:inout std_logic_vector(Data_width-1 downto 0);
			Address:out std_logic_vector(Address_width-1 downto 0);
			RD:out std_logic;
			WR:out std_logic;
			Ready:in std_logic;		
			ttt:out std_logic;																										--test
			r_data:out std_logic_vector(data_width-1 downto 0);										--test
			RST:in std_logic			
);
end component;
component write_read
port(
		RST:in std_logic;
		CLK:in std_logic;

		NIRO_IN:out std_logic;
		ALE:out std_logic;
--		TXDATA:out std_logic;
		NSTROBE:out std_logic;
		BE:out std_logic_vector(3 downto 0);		

		NSELECT:out std_logic;
		NRead:out std_logic;
		NWrite:out std_logic;
		RDY_IN:out std_logic;
		RDY_OUT:in std_logic;
		BLAST:  out std_logic;
		ADR:out std_logic_vector(ADR_width-1 downto 0);
		DQ:inout std_logic_vector(DQ_width-1 downto 0);
		
		DATA:inout std_logic_vector(DQ_width-1 downto 0);
		Address:in std_logic_vector(ADR_width-1 downto 0);
		RD:in std_logic;
		WR:in std_logic;		
		ttt:out std_logic;
		Ready:out std_logic
);
end component;
component read_fiber
port(
		RESET  :in std_logic;
		PASSENB:out std_logic;
		RXDATA :in std_logic;
		RXCNTL :in std_logic;
		RXFLAG :in std_logic;
		RXREADY:in std_logic;
		RXERROR:in std_logic;
		RXCLK0 :in std_logic;
		RXDSLIP:in std_logic;
--		REFCLK :out std_logic;
		RX     :in std_logic_vector(rx_width-1 downto 0);
		WBBB   :out std_logic_vector(data_width-1 downto 0);			--test
		M_clk  :in std_logic;
		RDATA  :out std_logic_vector(data_width-1 downto 0);
		RD     :in std_logic;
		RB     :in std_logic_vector(mem_address_out_width-1 downto 0);
		READY  :out std_logic 
);
end component;
component write_fiber
port(
		CLK:in std_logic;
		RST:in std_logic;
		WD:in std_logic;
		DATA_in:in std_logic_vector(data_width-1 downto 0);
		WB:in std_logic_vector(mem_address_width-1 downto 0);
		Full:out std_logic;
		TXDATA:out std_logic;
		RBBB:out std_logic_vector(data_width-1 downto 0);									--test
		TX:out std_logic_vector(tx_width-1 downto 0)
--		TCLK:out std_logic
);
end component;
--component dpram1
--port(
--   d : in std_logic_vector(data_width-1 downto 0);		--data input
--   rd : in std_logic;														--read command rising_edge is active
--   we : in std_logic;														--write command rising_edge is active
--   a:in std_logic_vector(mem_address_width-1 downto 0);	--write address
--   b:in std_logic_vector(mem_address_width-1 downto 0);	--read address
--   full  : out std_logic;												--indicate the mem is full  1
--   empty : out std_logic;												--indicate the mem is empty 0
--   q : out std_logic_vector(data_width-1 downto 0)		--read out the data
--);
--end component;
component reset
port(
			SET:IN std_logic;
			CLK:IN std_logic;
			RST:out std_logic
);
end component;
component suart
port(
		  clk		: IN std_logic;   
  		resetL	: IN std_logic;   
  		bclk	: OUT std_logic;   

  		-- Trasmitter
	  	txd		: OUT std_logic;   
	  	xbuf	: IN std_logic_vector(7 DOWNTO 0);   
	  	xmit_cmd	: IN std_logic;   
	  	xmit_done	: OUT std_logic;   

	  	-- Receiver
			rxd		: IN std_logic;   
			rbuf	: OUT std_logic_vector(7 DOWNTO 0);   
  		rec_ready	: OUT std_logic   
);
end component;
signal mem_in_data:std_logic_vector(data_width-1 downto 0);
signal mem_in_address:std_logic_vector(mem_address_width-1 downto 0);
signal mem_wr:std_logic;
signal mem_full:std_logic;
signal mem_out_data:std_logic_vector(data_width-1 downto 0);
signal mem_out_address:std_logic_vector(mem_address_out_width-1 downto 0);
signal mem_rd:std_logic;
signal mem_empty:std_logic;
signal data:std_logic_vector(DQ_width-1 downto 0);
signal address:std_logic_vector(ADR_width-1 downto 0);
signal blast_in:std_logic;
signal rd:std_logic;
signal wr:std_logic;
signal ready:std_logic;
signal Rest,RT:std_logic;
signal ttt,ttt1:std_logic;

signal uart_clk:std_logic;
signal sbuf:std_logic_vector(7 downto 0);
signal s_cmd:std_logic;
signal s_done:std_logic;
signal rbuf:std_logic_vector(7 downto 0);
signal r_done:std_logic;
signal data_s:std_logic_vector(7 downto 0);
signal flag,flag0,flag1,flag2,s_flag:std_logic;
signal data_C,data_buf,r_data,RBBB,WBBB:std_logic_vector(DQ_width-1 downto 0);
signal enable_w,enable_r:std_logic;
subtype ntype is natural range 0 to 3;
signal n:ntype;
type states is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11);
signal state,next_state:states;

begin
M(0)<= mem_empty;
M(1)<= mem_empty;
--U1:dpram1 port map(
--										d=>mem_in_data,
--										RD=>mem_rd,
--										WE=>mem_wr,
--										a =>mem_in_address,
--										b =>mem_out_address,
--										full=>mem_full,
--										empty=>mem_empty,
--										q =>mem_out_data
--);
Rest <= RT and RST;
U11:write_fiber port map(
													CLK => clk,
													RST => Rest,
													WD  => mem_wr,
													DATA_in => mem_in_data,
													WB  => mem_in_address,
													full=> mem_full,
													TXDATA=>TXDATA,
													RBBB=>RBBB,
													TX  => TX
--													TCLK=> TCLK
);
U12:read_fiber port map(
													RESET=> Rest,
													PASSENB => PASSENB,
													RXDATA  => RXDATA,
													RXCNTL  => RXCNTL,
													RXFLAG  => RXFLAG,
													RXREADY => RXREADY,
													RXERROR => RXERROR,
													RXCLK0  => RXCLK0,
													RXDSLIP => RXDSLIP,
--													REFCLK  => REFCLK,
													RX      => RX,
													WBBB    => WBBB,
													M_clk   => clk,
													RDATA   => mem_out_data,
													RD      => mem_rd,
													RB      => mem_out_address,
													READY   => mem_empty
);
U2:control port map(
										MEM_IN_DATA =>mem_in_data,
										MEM_IN_ADDRESS =>mem_in_address,
										MEM_WR =>mem_wr,
										MEM_FULL=>mem_full,
										MEM_OUT_DATA=>mem_out_data,
										MEM_OUT_ADDRESS=>mem_out_address,
										MEM_RD => mem_rd,
										MEM_EMPTY => mem_empty,

										CLK =>clk,
										DATA=>data,
										Address => address,
										RD => rd,
										WR => wr,
										Ready =>ready,
										ttt => ttt1,
										r_data =>r_data,
										RST => Rest
);
U3:write_read port map(
											 RST => Rest,	
											 CLK => clk,
											 NIRO_IN => NIRO_IN,
											 ALE     => ALE,
--											 TXDATA  => TXDATA,											 
											 NSTROBE => NSTROBE,
											 BE      => BE,
											 NSELECT => NSELECT,
											 NRead   => NRead,
											 NWrite =>NWrite,
											 RDY_IN =>RDY_IN,
											 RDY_OUT=>RDY_OUT,
											 BLAST => BLAST,
											 ADR => ADR,
											 DQ => DQ,
											 DATA => data,
											 Address => Address,											 
											 RD => RD,
											 WR => WR,
											 ttt => ttt,
											 Ready => Ready
);
U4:reset port map(
									SET => RST,
									CLK => clk,
									RST => RT									
);
U5:suart port map(
									clk => clk,
									resetL=>Rest,
									bclk=>uart_clk,
									txd => txd,
									xbuf => sbuf,
									xmit_cmd => s_cmd,
									xmit_done=> s_done,
									rxd => rxd,
									rbuf => rbuf,
									rec_ready => r_done
);

statemachine:process(uart_clk,Rest)
begin
	if(Rest = '0') then
		state <= s0;
	elsif(uart_clk'event and uart_clk = '1') then
		state <= next_state;
	end if;
end process statemachine;
sendmachine:process(uart_clk,state)
begin
	if uart_clk'event and uart_clk = '1' then
		case state is
			when s0 => s_cmd <= '0';
								 if r_done = '1' then	
								 		if rbuf = "10101010" then 				--AA send 00 - FF												
								 				data_s <= (others=>'0');
								 				next_state <= s1;
								 		elsif rbuf = "01010101" then 
												next_state <= s4;							--55 write
								 		elsif rbuf = "01000100" then 
												next_state <= s6;							-- 44 read
								 		else next_state <= s0;
								 		end if;
								 else next_state <= s0;	
								 end if;		
			when s1 => sbuf <= data_s;										 
										 s_cmd <= '1';
										 next_state <= s2;
			when s2 => s_cmd <= '0';							 								 		
										 if s_done = '1' then 
										 		next_state <= s3;
										 		flag <='0';
										 else next_state <= s2;
										 end if;
			when s3 => if flag = '0' then
										 if data_s = "11111111" then
												next_state <= s0;
										 else data_s <= data_s + '1';
												 next_state <= s1; 	
										 end if;
												flag <= '1';
								 end if;
			when s4 =>	next_state <= s0;
			when s5 =>	next_state <= s0;    --write over
			when s6 =>	data_buf <= r_data; 	--RBBB; 		--r_data;	--WBBB; 
									next_state<= s7;
			when s7 => 	sbuf <= data_buf(31 downto 24);
									next_state <= s8;
			when s8 =>	s_cmd <= '1';															--send up
									s_flag<='0';
									next_state <= s9;						
			when s9 =>  s_cmd <= '0';		
									if s_flag = '0' then
											n <= n + 1;
											s_flag<='1';
									end if;							 								 											
									if s_done = '1' then 
										 		next_state <= s10;
								  else next_state <= s9;
									end if; 
			when s10=>	case n is
										when 1 => sbuf <= data_buf(23 downto 16);
															next_state <= s8;
										when 2 => sbuf <= data_buf(15 downto 8);
										          next_state <= s8;
										when 3 => sbuf <= data_buf(7 downto 0);
															next_state <= s8;
										when others =>flag2 <= '0'; 
																	next_state<=s11;					    										 
									end case;
			when s11 =>	next_state <= s0;							 								 			
			when others => next_state <= s0;							 								 			
			
		end case;
	end if;	
end process sendmachine;	
end str;