gain.v

FPGA verilog

module Gain
	(
		CLK,
		Pin,
		Pout,
		A,
		B,
		Result
	);

	input			CLK;
	input	[23:0]	Pin;
	input	[23:0]	Pout;
	input	[31:0]	A;
	input	[31:0]	B;
	output	[31:0]	Result;

	reg		[31:0]	Result;

	wire	[23:0]	numer,denom;
	
	wire	[38:0]	DivResult;
	//Gain = (Pout+A-B)/(Pin+A)
	//B = A-B
	lpm_divide_gain	 GainDivide(
			.clock(CLK),
			.clken(1'b1),
			.numer({numer[23]?24'h000001:numer,15'h0000}),
			.denom(denom),
			.quotient(DivResult));

	lpm_add_signed_24	b2v_add1(.dataa(Pout),
						.datab(B[23:0]),
						.result(numer));

	lpm_add_signed_24	b2v_add2(.dataa(Pin),
						.datab(A[23:0]),
						.result(denom));					
	
	always @(posedge CLK)
	begin
		Result = DivResult[31:0];
	end
	
endmodule