cnt10.map.rpt

基于fpga和sopc的用VHDL语言编写的EDA含异步清0和同步时钟使能的加法计数器

; H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt4/EXPT43_cnt10/db/cntr_vt7.tdf        ; yes             ;
; H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt4/EXPT43_cnt10/db/cntr_dn7.tdf        ; yes             ;
; e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd                ; yes             ;
; e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd                   ; yes             ;
; e:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf                ; yes             ;
; e:/altera/quartus41/libraries/megafunctions/declut.inc                    ; yes             ;
; H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt4/EXPT43_cnt10/db/decode_9ie.tdf      ; yes             ;
; e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd                 ; yes             ;
; H:/ZX1C3_1C6demo/EDA_SOPC1C6_12/Chpt4/EXPT43_cnt10/db/cntr_ed8.tdf        ; yes             ;
+---------------------------------------------------------------------------+-----------------+


+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                  ;
+-----------------------------------+--------------------------+
; Resource                          ; Usage                    ;
+-----------------------------------+--------------------------+
; Logic cells                       ; 350                      ;
; Total combinational functions     ; 244                      ;
; Total 4-input functions           ; 110                      ;
; Total 3-input functions           ; 55                       ;
; Total 2-input functions           ; 32                       ;
; Total 1-input functions           ; 44                       ;
; Total 0-input functions           ; 3                        ;
; Combinational cells for routing   ; 0                        ;
; Total registers                   ; 251                      ;
; Total logic cells in carry chains ; 55                       ;
; I/O pins                          ; 8                        ;
; Total memory bits                 ; 9216                     ;
; Maximum fan-out node              ; altera_internal_jtag~TDO ;
; Maximum fan-out                   ; 184                      ;
; Total fan-out                     ; 1709                     ;
; Average fan-out                   ; 4.59                     ;
+-----------------------------------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                 ;
+--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name                                                                                                         ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF  ;
+--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; sld_signaltap:cnts|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_8g82:auto_generated|ALTSYNCRAM ; M4K  ; Simple Dual Port ; 1024         ; 9            ; 1024         ; 9            ; 9216 ; None ;
+--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Mon Aug 29 13:11:57 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off CNT10 -c cnt10
Info: Found 2 design units, including 1 entities, in source file cnt10.VHD
    Info: Found design unit 1: CNT10-behav
    Info: Found entity 1: CNT10
Info: Found 3 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_signaltap.vhd
    Info: Found design unit 1: sld_signaltap_pack
    Info: Found design unit 2: sld_signaltap-rtl
    Info: Found entity 1: sld_signaltap
Info: Found 14 design units, including 7 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_ela_control.vhd
    Info: Found design unit 1: sld_ela_control-rtl
    Info: Found design unit 2: sld_ela_level_seq_mgr-rtl
    Info: Found design unit 3: sld_ela_state_machine-rtl
    Info: Found design unit 4: sld_ela_seg_state_machine-rtl
    Info: Found design unit 5: sld_ela_post_trigger_counter-rtl
    Info: Found design unit 6: sld_ela_segment_mgr-rtl
    Info: Found design unit 7: sld_ela_basic_multi_level_trigger-rtl
    Info: Found entity 1: sld_ela_control
    Info: Found entity 2: sld_ela_level_seq_mgr
    Info: Found entity 3: sld_ela_state_machine
    Info: Found entity 4: sld_ela_seg_state_machine
    Info: Found entity 5: sld_ela_post_trigger_counter
    Info: Found entity 6: sld_ela_segment_mgr
    Info: Found entity 7: sld_ela_basic_multi_level_trigger
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Found 4 design units, including 2 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_mbpmg.vhd
    Info: Found design unit 1: sld_mbpmg-rtl
    Info: Found design unit 2: sld_sbpmg-rtl
    Info: Found entity 1: sld_mbpmg
    Info: Found entity 2: sld_sbpmg
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Warning: LPM_MODULUS input va