tri2.vhd

来自「基于fpga和sopc的用VHDL语言编写的EDA含异步清0和同步时钟使能的加法」· VHDL 代码 · 共 13 行

library ieee;
use ieee.std_logic_1164.all;
entity tri2 is
port (ctl : in  std_logic;
         d2, d3 :  in std_logic_vector(7 downto 0);
        q : out std_logic_vector(7 downto 0)   );
end tri2;
architecture body_tri of tri2 is
begin
 q <= d2   when ctl='0' else "00000000" ;
 q <= d3   when ctl='1' else "00000000" ;
 end body_tri;