cnt10.map.summary

来自「基于fpga和sopc的用VHDL语言编写的EDA含异步清0和同步时钟使能的加法」· SUMMARY 代码 · 共 12 行

Flow Status : Successful - Mon Aug 29 13:12:15 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : cnt10
Top-level Entity Name : CNT10
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Production
Total logic elements : 350
Total pins : 12
Total memory bits : 9,216
Total PLLs : 0