pc_gen.v

32位RISC单片机verilog源码内包含说明文档经过他人测试通过

module pc_gen(clk,reset,mux_pc,mux_pc_id,rx,next,ret_addr,expt_addr,imm_id,pc);

input clk;
input reset;
input mux_pc_id;
input [2:0]  mux_pc;
input [31:0] rx;
input [31:0] imm_id;
input [31:0] ret_addr;
input [31:0] expt_addr;
output [31:0] next;
output [31:0] pc;

reg [31:0]   pc;
wire [31:0]  btc_addr;
wire [31:0] pc_rx,imm_oo;

assign pc_rx=(mux_pc_id)? rx : next;
assign imm_oo={imm_id[29:0],2'b00};//shift left 2  
assign btc_addr=pc_rx+imm_oo;
assign next=pc+4;

always @(posedge clk or posedge reset )begin
  if(reset)pc<=32'h00000000;
  else 
    casex(mux_pc)      //mux_pc={int,btc,return}
    3'b1xx:pc<=expt_addr;
    3'b010:pc<=btc_addr;
    3'b001:pc<=ret_addr;
    3'b000:pc<=next;    
    default:pc<=pc+4;
  endcase
end
endmodule