regfile.v

来自「32位RISC单片机verilog源码内包含说明文档经过他人测试通过」· Verilog 代码 · 共 66 行

module regfile(clk,s1,s2,dest,out1,out2,data_in,r31_wr_en,reg_wr_en,pc_buf);
input clk;
input r31_wr_en;//link register write
input reg_wr_en;
input [4:0]  s1;
input [4:0]  s2;
input [4:0]  dest;
input [31:0] data_in;
input [31:0] pc_buf;
output [31:0] out1;
output [31:0] out2;

reg [31:0] out1;            
reg [31:0] out2;
reg [31:0] r1,r2,r3,r31;
 
always @(negedge clk)begin
   case(s1)
  5'h0:out1<=32'h0000_0000;
  5'h1:out1<=r1;  
  5'h2:out1<=r2;  
  5'h3:out1<=r3;   
  /* 5'h4:out1<=r4; 
  5'h5:out1<=r5;  
  5'h6:out1<=r6;  
  5'h7:out1<=r7;  */
  5'h1f:out1<=r31;
  default out1<=32'h0000_0000;
  endcase
end

always @(negedge clk)begin
  case(s2)
  5'h0 :out2<=32'h0000_0000;
  5'h1 :out2<=r1;  
  5'h2 :out2<=r2;  
  5'h3 :out2<=r3;  
  /* 5'h4 :out2<=r4; 
  5'h5 :out2<=r5;  
  5'h6 :out2<=r6;  
  5'h7 :out2<=r7; */
  5'h1f:out2<=r31;
  default out2<=32'h0000_0000;
  endcase
end

always @(posedge clk)begin
  if(reg_wr_en)begin
    case(dest) 
    //5'h0://r0<=32'h0000_0000;
    5'h1:r1<=data_in;  
    5'h2:r2<=data_in;  
    5'h3:r3<=data_in; 
    /* 5'h4:r4<=data_in; 
    5'h5:r5<=data_in;  
    5'h6:r6<=data_in;  
    5'h7:r7<=data_in; */
	 default r1<=r1;
    endcase
  end
  
  if(r31_wr_en)r31<=pc_buf;    //R31 is link register
end

endmodule