writeback.v

来自「32位RISC单片机verilog源码内包含说明文档经过他人测试通过」· Verilog 代码 · 共 14 行

module write_back(wb,data_ram,data_alu,data_out);
input wb;
input [31:0] data_ram;
input [31:0] data_alu;
output [31:0] data_out;

reg [31:0] data_out;

always @(wb or data_ram or data_alu)begin
  if(!wb)data_out<=data_ram;
  else  data_out<=data_alu;
end

endmodule