alu.v

32位RISC单片机verilog源码内包含说明文档经过他人测试通过

//`timescale 1ns/1ps

module alu(  op, s1, s2, imm_32, imm_en, alu_o, flag_o,
             mux_1, mux_2, fdata_ex, fdata_mem, s2_fwd ,c_in
           );
                    
input [3:0] op;             
input imm_en;
input [1:0] mux_1, mux_2;                                                      
input [31:0] s1, s2, imm_32;
input [31:0] fdata_ex, fdata_mem; //forwarded  data  
input c_in;

output [31:0] s2_fwd;
output [31:0] alu_o;
output [4:0] flag_o;

reg  [31:0] alu_o;
reg  [31:0] s2_fwd;
reg  [31:0] data1, data2;
reg carry;
reg over;
wire [31:0] a;
/***********************wire for flag*********************/
wire [4:0] flag_o;
wire c;  //carry
wire z;  //zero
wire n;  //negative
wire v;  //over

parameter op_nop  = 4'h0;
parameter op_add  = 4'h1;
parameter op_addc = 4'h2;
parameter op_sub  = 4'h3;
parameter op_subc = 4'h4;
parameter op_and  = 4'h5;
parameter op_or   = 4'h6;
parameter op_not  = 4'h7;
parameter op_lsl  = 4'h8;
parameter op_lsr  = 4'h9; //logic shift right
parameter op_asr  = 4'ha; //arithmetic shift right
parameter op_ror  = 4'hb; //rotate right
parameter op_rol  = 4'hc;

/***************selcet data for RAM*******************/
always @(mux_2 or s2 or fdata_ex or fdata_mem) begin
  casex (mux_2)
    2'b00: s2_fwd = s2; 
    2'b01: s2_fwd = fdata_mem;
	 2'b10: s2_fwd = fdata_ex;
	 default: s2_fwd = 32'h00000000;
 endcase
end

/****************select data_1 for alu operation*************/
always @(mux_1 or s1 or fdata_ex or fdata_mem) begin
  case (mux_1)
    2'b00: data1 = s1;
    2'b01: data1 = fdata_mem;
	 2'b10: data1 = fdata_ex;
	 default: data1 = 32'h00000000;
  endcase
end

/****************select data2 for alu operation*************/
always @(imm_en or s2_fwd or imm_32) begin
  casex (imm_en)
    1'b1: data2 = imm_32;
    1'b0: data2 = s2_fwd; 
	 default: data2 = 32'h00000000;
 endcase
end

always @(data2 or data1 or op or c_in)
	case (op)
	   op_and  :  { carry , over , alu_o } = { 2'b00 , data1 & data2 };
      op_or   :  { carry , over , alu_o } = { 2'b00 , data1 | data2 };
		op_not  :  { carry , over , alu_o } = { 2'b00 , ~data2 };
      op_add  :  { carry , over , alu_o } = { data2[31] , data2 } + { data1[31] , data1 }; 
      op_addc :  { carry , over , alu_o } = { data2[31] , data2 } + { data1[31] , data1 }+c_in;
      op_sub  :  { carry , over , alu_o } = { data1[31] , data1 } - { data2[31] , data2 }; 
      op_subc :  { carry , over , alu_o } = { data1[31] , data1 } - { data2[31] , data2 }-c_in;
      op_lsr  :  { carry , alu_o } = { 1'b0 , data1 } >> data2[4:0];
      op_lsl  :  { carry , alu_o } = { data1[31] , data1 } << data2[4:0];
      op_asr  :  { carry , alu_o } = { data1[31] , data1 } >>> data2[4:0];
      op_ror  :  { carry , alu_o } = { data1[0] , data1[0] , data1[31:1] };
      op_rol  :  { carry , alu_o } = { data1[30] , data1[30:0] , data1[31] };      
		default :  alu_o = 32'h00000000;
	endcase
	
assign c = carry; 
assign n = alu_o[31];
assign z = !alu_o[31:0];
assign v = over^alu_o[31];
assign flag_o = {c,z,n,v,1'b0};
endmodule