pc_gen_test.v

32位RISC单片机verilog源码内包含说明文档经过他人测试通过

`timescale 1ns/1ps

module pc_gen_test;
    reg clk = 1'b0;
    reg reset = 1'b0;
    reg [2:0] mux_pc = 3'b000;
    reg mux_pc_id = 1'b0;
    reg [31:0] rx = 32'b00000000000000000000000001010000;
    wire [31:0] next;
    reg [31:0] ret_addr = 32'b00000000000000000000000000100100;
    reg [31:0] expt_addr = 32'b00000000000000000000000001111000;
    reg [31:0] imm_id = 32'b00000000000000000000000000000100;
    wire [31:0] pc;

    parameter PERIOD = 200;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;

    initial    // Clock process for clk
    begin
        #OFFSET;
        forever
        begin
            clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

    pc_gen UUT (
        .clk(clk),
        .reset(reset),
        .mux_pc(mux_pc),
        .mux_pc_id(mux_pc_id),
        .rx(rx),
        .next(next),
        .ret_addr(ret_addr),
        .expt_addr(expt_addr),
        .imm_id(imm_id),
        .pc(pc));

    
    initial begin  
        
        #5200 // Final time:  5200 ns
        $stop;
    end

    initial begin
        
        #85;
        reset = 1'b1;
   
        #200;
        reset = 1'b0;

        #1000;
        mux_pc = 3'b010;

        #200;
        mux_pc = 3'b000;

        #400;
        mux_pc = 3'b001;

        #200;
        mux_pc = 3'b000;

        #600;
        mux_pc_id = 1'b1;

        #200;
        mux_pc = 3'b010;

        #200;
        mux_pc = 3'b000;

        #400;
        mux_pc = 3'b001;

        #200;
        mux_pc = 3'b000;

    end

endmodule


    pc_gen UUT (
        .clk(clk),
        .reset(reset),
        .mux_pc(mux_pc),
        .mux_pc_id(mux_pc_id),
        .rx(rx),
        .next(next),
        .ret_addr(ret_addr),
        .expt_addr(expt_addr),
        .imm_id(imm_id),
        .pc(pc));

    integer TX_FILE = 0;
    integer TX_ERROR = 0;
    
    initial begin  // Open the results file...
        TX_FILE = $fopen("results.txt");
        #4200 // Final time:  4200 ns
        if (TX_ERROR == 0) begin
            $display("No errors or warnings.");
            $fdisplay(TX_FILE, "No errors or warnings.");
        end else begin
            $display("%d errors found in simulation.", TX_ERROR);
            $fdisplay(TX_FILE, "%d errors found in simulation.", TX_ERROR);
        end
        $fclose(TX_FILE);
        $stop;
    end

    initial begin
        // -------------  Current Time:  85ns
        #85;
        reset = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  285ns
        #200;
        reset = 1'b0;
        // -------------------------------------
        // -------------  Current Time:  885ns
        #600;
        mux_pc = 3'b010;
        // -------------------------------------
        // -------------  Current Time:  1085ns
        #200;
        mux_pc = 3'b000;
        // -------------------------------------
        // -------------  Current Time:  1685ns
        #600;
        mux_pc = 3'b001;
        // -------------------------------------
        // -------------  Current Time:  1885ns
        #200;
        mux_pc = 3'b000;
        // -------------------------------------
        // -------------  Current Time:  2085ns
        #200;
        mux_pc_id = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  2285ns
        #200;
        mux_pc = 3'b010;
        // -------------------------------------
        // -------------  Current Time:  2485ns
        #200;
        mux_pc = 3'b000;
        // -------------------------------------
        // -------------  Current Time:  3085ns
        #600;
        mux_pc = 3'b001;
        // -------------------------------------
    end

    task CHECK_next;
        input [31:0] NEXT_next;

        #0 begin
            if (NEXT_next !== next) begin
                $display("Error at time=%dns next=%b, expected=%b", $time, next, NEXT_next);
                $fdisplay(TX_FILE, "Error at time=%dns next=%b, expected=%b", $time, next, NEXT_next);
                $fflush(TX_FILE);
                TX_ERROR = TX_ERROR + 1;
            end
        end
    endtask
    task CHECK_pc;
        input [31:0] NEXT_pc;

        #0 begin
            if (NEXT_pc !== pc) begin
                $display("Error at time=%dns pc=%b, expected=%b", $time, pc, NEXT_pc);
                $fdisplay(TX_FILE, "Error at time=%dns pc=%b, expected=%b", $time, pc, NEXT_pc);
                $fflush(TX_FILE);
                TX_ERROR = TX_ERROR + 1;
            end
        end
    endtask

endmodule