phase_detector.v

来自「使用virlog语言编写的一个 锁相环的程序。可直接在cpld中应用。」· Verilog 代码 · 共 26 行

module phase_detector
	(
		clka,
		clkb,
		out_u, 
		out_d
	);

	input clka, clkb;
	output out_u, out_d;
   
	wire sr1r, sr2r, sr1q, sr2q, sr1q_, sr2q_, intreg ;
	wire out_u, out_d;

	nand nand1(sr1r, clka, out_u);
	nand nand2(sr1q, sr1r, sr1q_);
	nand nand3(sr1q_, sr1q, intreg);
	nand nand4(sr2r, clkb, out_d);
	nand nand5(sr2q, sr2r, sr2q_);
	nand nand6(sr2q_, sr2q, intreg);
	nand nand7(intreg, sr1r, sr2r, sr1q, sr2q);
	nand nand8(out_u, sr1r, sr1q, intreg);
	nand nand9(out_d, sr2r, sr2q, intreg);
	
endmodule