phase_detector_top.tan.summary

来自「使用virlog语言编写的一个 锁相环的程序。可直接在cpld中应用。」· SUMMARY 代码 · 共 77 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.240 ns
From           : rst
To             : fq_divider:fq_divider_10m|q
From Clock     : --
To Clock       : clk_10m
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.195 ns
From           : dff3
To             : out_d
From Clock     : clk_10m
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 7.165 ns
From           : rst
To             : fpga_rst
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.318 ns
From           : rst
To             : fq_divider:fq_divider_13_75m|q
From Clock     : --
To Clock       : clk_13_75m
Failed Paths   : 0

Type           : Clock Setup: 'clk_13_75m'
Slack          : N/A
Required Time  : None
Actual Time    : 138.10 MHz ( period = 7.241 ns )
From           : fq_divider:fq_divider_13_75m|cnt[4]
To             : fq_divider:fq_divider_13_75m|cnt[7]
From Clock     : clk_13_75m
To Clock       : clk_13_75m
Failed Paths   : 0

Type           : Clock Setup: 'clk_10m'
Slack          : N/A
Required Time  : None
Actual Time    : 152.51 MHz ( period = 6.557 ns )
From           : fq_divider:fq_divider_10m|cnt[4]
To             : fq_divider:fq_divider_10m|cnt[0]
From Clock     : clk_10m
To Clock       : clk_10m
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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