phase_detector_top.fit.summary

使用virlog语言编写的一个 锁相环的程序。可直接在cpld中应用。

Fitter Status : Successful - Mon Jun 18 14:42:06 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : phase_detector_top
Top-level Entity Name : phase_detector_top
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
Total logic elements : 40 / 240 ( 17 % )
Total pins : 26 / 80 ( 33 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )