ver6.chp

TOSHIBA公司的射频卡VERILOGHDL代码 包括TOP 顶层文件

=========
Chip ver6
=========

Summary Information:
--------------------
Type: Initial implementation
Source: up to date
Status: 0 errors, 41 warnings, 8 messages

Target Information:
-------------------
Vendor: Xilinx
Family: XC4000XL
Device: 4085XLBG432
Speed: xl-1

Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: Low
Frequency: 50 MHz
Is module: No
Keep io pads: No
Number of flip-flops: 107
Number of latches: 0

Chip Design Hierarchy:
----------------------
XilinxU: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\xilinxx.v
  MainU: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\mainx.v
    CRCU5: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\crc2x.v
    ClockDivU: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\clkdivx.v
    CRCU6: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\crc3x.v
    SendU: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\sendx.v
    RecvU: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\recvx.v

Primitive reference count:
--------------------------
BUFG          3
IBUF          2

Clocks:
-------
                           Required  Estimated                       
Period   Rise     Fall     Freq      Freq       Signal               
(ns)     (ns)     (ns)     (MHz)     (MHz)                           
...............................................................
 20        0       10       50.00     -1.00     default              
 -1       -1       -1      -1000.00  100.00     mainClk0             
 -1       -1       -1      -1000.00  100.00     eeclk0               
 -1       -1       -1      -1000.00  100.00     rfClk0               

Timing Groups:
--------------
                                                              
                                                              
Name                 Description                              
............................................................
(I)                  Input ports                              
(O)                  Output ports                             
(RC,mainClk0)        Clocked by rising edge of mainClk0       
(RC,eeclk0)          Clocked by rising edge of eeclk0         
(RC,rfClk0)          Clocked by rising edge of rfClk0         

Timing Path Groups:
-------------------
                                          Required   Estimated  
                                          Delay      Delay      
From                 To                   (ns)       (ns)       
............................................................
(I)                  (O)                   20.00      -1.00     
(I)                  (RC,mainClk0)         20.00      -1.00     
(I)                  (RC,eeclk0)           20.00      -1.00     
(I)                  (RC,rfClk0)           20.00      -1.00     
(RC,mainClk0)        (O)                   20.00      -1.00     
(RC,mainClk0)        (RC,mainClk0)         20.00      -1.00     
(RC,mainClk0)        (RC,eeclk0)           20.00      -1.00     
(RC,mainClk0)        (RC,rfClk0)           20.00      -1.00     
(RC,eeclk0)          (O)                   20.00      -1.00     
(RC,eeclk0)          (RC,mainClk0)         20.00      -1.00     
(RC,eeclk0)          (RC,eeclk0)           20.00      -1.00     
(RC,eeclk0)          (RC,rfClk0)           20.00      -1.00     
(RC,rfClk0)          (O)                   20.00      -1.00     
(RC,rfClk0)          (RC,mainClk0)         20.00      -1.00     
(RC,rfClk0)          (RC,eeclk0)           20.00      -1.00     
(RC,rfClk0)          (RC,rfClk0)           20.00      -1.00     

Input Port Timing:
------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       To-Group             
............................................................
breset0               20.00      -1.00     (RC,mainClk0)        
rfClk0                20.00      -1.00     (RC,mainClk0)        
rfData                20.00      -1.00     (RC,mainClk0)        
sramDT<7>             20.00      -1.00     (RC,mainClk0)        
sramDT<6>             20.00      -1.00     (RC,mainClk0)        
sramDT<5>             20.00      -1.00     (RC,mainClk0)        
sramDT<4>             20.00      -1.00     (RC,mainClk0)        
sramDT<3>             20.00      -1.00     (RC,mainClk0)        
sramDT<2>             20.00      -1.00     (RC,mainClk0)        
sramDT<1>             20.00      -1.00     (RC,mainClk0)        
sramDT<0>             20.00      -1.00     (RC,mainClk0)        

Output Port Timing:
-------------------
                     Required   Estimated                       
Port                 Delay      Slack                           
Name                 (ns)       (ns)       From-Group           
............................................................
rfOut                 20.00      -1.00     (RC,mainClk0)        
sramcs                20.00      -1.00     (RC,mainClk0)        
sramoe                20.00      -1.00     (RC,mainClk0)        
sramwe                20.00      -1.00     (RC,mainClk0)        
sramAD<18>            20.00      -1.00     (RC,mainClk0)        
sramAD<17>            20.00      -1.00     (RC,mainClk0)        
sramAD<16>            20.00      -1.00     (RC,mainClk0)        
sramAD<15>            20.00      -1.00     (RC,mainClk0)        
sramAD<14>            20.00      -1.00     (RC,mainClk0)        
sramAD<13>            20.00      -1.00     (RC,mainClk0)        
sramAD<12>            20.00      -1.00     (RC,mainClk0)        
sramAD<11>            20.00      -1.00     (RC,mainClk0)        
sramAD<10>            20.00      -1.00     (RC,mainClk0)        
sramAD<9>             20.00      -1.00     (RC,mainClk0)        
sramAD<8>             20.00      -1.00     (RC,mainClk0)        
sramAD<7>             20.00      -1.00     (RC,mainClk0)        
sramAD<6>             20.00      -1.00     (RC,mainClk0)        
sramAD<5>             20.00      -1.00     (RC,mainClk0)        
sramAD<4>             20.00      -1.00     (RC,mainClk0)        
sramAD<3>             20.00      -1.00     (RC,mainClk0)        
sramAD<2>             20.00      -1.00     (RC,mainClk0)        
sramAD<1>             20.00      -1.00     (RC,mainClk0)        
sramAD<0>             20.00      -1.00     (RC,mainClk0)        
sramDT<7>             20.00      -1.00     (RC,mainClk0)        
sramDT<6>             20.00      -1.00     (RC,mainClk0)        
sramDT<5>             20.00      -1.00     (RC,mainClk0)        
sramDT<4>             20.00      -1.00     (RC,mainClk0)        
sramDT<3>             20.00      -1.00     (RC,mainClk0)        
sramDT<2>             20.00      -1.00     (RC,mainClk0)        
sramDT<1>             20.00      -1.00     (RC,mainClk0)        
sramDT<0>             20.00      -1.00     (RC,mainClk0)