anal.out

来自「TOSHIBA公司的射频卡VERILOGHDL代码 包括TOP 顶层文件」· OUT 代码 · 共 5 行

Loading db file 'C:/App/Fndtn/Synth/lib/libraries/syn/gtech.db'
Reading in the Synopsys verilog primitives.
C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v:
Warning: Parameter range specification is only meaningful to synthesis. Different result may exist from simulations near symbol "]" on line 65 in file mainx.v. (VE-122)