sendu.out

来自「TOSHIBA公司的射频卡VERILOGHDL代码 包括TOP 顶层文件」· OUT 代码 · 共 23 行

Inferred memory devices in process 
	in routine SendU line 14 in file
         'C:/prj/verilog/try/ticket2/c/t6n76_3/sendx.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     outBuf_reg      | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
|     outCnt_reg      | Flip-flop |   3   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================

outBuf_reg (width 8)
--------------------
    set/reset/toggle: none


outCnt_reg (width 3)
--------------------
    set/reset/toggle: none


Writing to hnl file 'c:\prj\Verilog\Try\Ticket2\c\T6N76_3\t6n76_3/workdirs/WORK/SendU.hnl'