clockdivu.out

来自「TOSHIBA公司的射频卡VERILOGHDL代码 包括TOP 顶层文件」· OUT 代码 · 共 30 行

Inferred memory devices in process 
	in routine ClockDivU line 18 in file
         'C:/prj/verilog/try/ticket2/c/t6n76_3/clkdivx.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|        c_reg        | Flip-flop |   7   |  Y  | N  | Y  | N  | N  | N  | N  |
|     mainClk_reg     | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | Y  |
|        s_reg        | Flip-flop |   4   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================

c_reg (width 7)
---------------
    Async-reset: brst'


mainClk_reg
-----------
    Async-reset: brst'
    Sync-toggle: c<1>' c<2> c<3>' c<4> eeclk' + div eeclk'


s_reg (width 4)
---------------
    Async-reset: brst'


Writing to hnl file 'c:\prj\Verilog\Try\Ticket2\c\T6N76_3\t6n76_3/workdirs/WORK/ClockDivU.hnl'