📄 ver6-optimized.chp
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Chip ver6-Optimized
===================
Summary Information:
--------------------
Type: Optimized implementation
Source: ver6, up to date
Status: 8 errors, 0 warnings, 0 messages
Export: not exported since last optimization
Target Information:
-------------------
Vendor: Xilinx
Family: XC4000XL
Device: 4085XLBG432
Speed: xl-1
Chip Parameters:
----------------
Optimize for: Speed
Optimization effort: Low
Frequency: 50 MHz
Is module: No
Keep io pads: No
Number of flip-flops: 107
Number of latches: 0
Chip Design Hierarchy:
----------------------
XilinxU: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\xilinxx.v
MainU: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\mainx.v
CRCU5: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\crc2x.v
ClockDivU: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\clkdivx.v
CRCU6: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\crc3x.v
SendU: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\sendx.v
RecvU: defined in c:\prj\verilog\try\ticket2\c\t6n76_3\recvx.v
Primitive reference count:
--------------------------
BUFG 3
IBUF 2
Clocks:
-------
Required Estimated
Period Rise Fall Freq Freq Signal
(ns) (ns) (ns) (MHz) (MHz)
...............................................................
20 0 10 50.00 -1.00 default
-1 -1 -1 -1000.00 100.00 mainClk0
-1 -1 -1 -1000.00 100.00 eeclk0
-1 -1 -1 -1000.00 100.00 rfClk0
Timing Groups:
--------------
Name Description
............................................................
(I) Input ports
(O) Output ports
(RC,mainClk0) Clocked by rising edge of mainClk0
(RC,eeclk0) Clocked by rising edge of eeclk0
(RC,rfClk0) Clocked by rising edge of rfClk0
Timing Path Groups:
-------------------
Required Estimated
Delay Delay
From To (ns) (ns)
............................................................
(I) (O) n/a n/a
(I) (RC,mainClk0) n/a n/a
(I) (RC,eeclk0) n/a n/a
(I) (RC,rfClk0) n/a n/a
(RC,mainClk0) (O) n/a n/a
(RC,mainClk0) (RC,mainClk0) n/a n/a
(RC,mainClk0) (RC,eeclk0) n/a n/a
(RC,mainClk0) (RC,rfClk0) n/a n/a
(RC,eeclk0) (O) n/a n/a
(RC,eeclk0) (RC,mainClk0) n/a n/a
(RC,eeclk0) (RC,eeclk0) n/a n/a
(RC,eeclk0) (RC,rfClk0) n/a n/a
(RC,rfClk0) (O) n/a n/a
(RC,rfClk0) (RC,mainClk0) n/a n/a
(RC,rfClk0) (RC,eeclk0) n/a n/a
(RC,rfClk0) (RC,rfClk0) n/a n/a
Input Port Timing:
------------------
Required Estimated
Port Delay Slack
Name (ns) (ns) To-Group
............................................................
breset0 n/a n/a (RC,mainClk0)
rfClk0 n/a n/a (RC,mainClk0)
rfData n/a n/a (RC,mainClk0)
sramDT<7> n/a n/a (RC,mainClk0)
sramDT<7> n/a n/a (RC,mainClk0)
sramDT<7> n/a n/a (RC,mainClk0)
sramDT<7> n/a n/a (RC,mainClk0)
sramDT<6> n/a n/a (RC,mainClk0)
sramDT<6> n/a n/a (RC,mainClk0)
sramDT<6> n/a n/a (RC,mainClk0)
sramDT<6> n/a n/a (RC,mainClk0)
sramDT<5> n/a n/a (RC,mainClk0)
sramDT<5> n/a n/a (RC,mainClk0)
sramDT<5> n/a n/a (RC,mainClk0)
sramDT<5> n/a n/a (RC,mainClk0)
sramDT<4> n/a n/a (RC,mainClk0)
sramDT<4> n/a n/a (RC,mainClk0)
sramDT<4> n/a n/a (RC,mainClk0)
sramDT<4> n/a n/a (RC,mainClk0)
sramDT<3> n/a n/a (RC,mainClk0)
sramDT<3> n/a n/a (RC,mainClk0)
sramDT<3> n/a n/a (RC,mainClk0)
sramDT<3> n/a n/a (RC,mainClk0)
sramDT<2> n/a n/a (RC,mainClk0)
sramDT<2> n/a n/a (RC,mainClk0)
sramDT<2> n/a n/a (RC,mainClk0)
sramDT<2> n/a n/a (RC,mainClk0)
sramDT<1> n/a n/a (RC,mainClk0)
sramDT<1> n/a n/a (RC,mainClk0)
sramDT<1> n/a n/a (RC,mainClk0)
sramDT<1> n/a n/a (RC,mainClk0)
sramDT<0> n/a n/a (RC,mainClk0)
sramDT<0> n/a n/a (RC,mainClk0)
sramDT<0> n/a n/a (RC,mainClk0)
sramDT<0> n/a n/a (RC,mainClk0)
Output Port Timing:
-------------------
Required Estimated
Port Delay Slack
Name (ns) (ns) From-Group
............................................................
rfOut n/a n/a (RC,mainClk0)
sramcs n/a n/a (RC,mainClk0)
sramoe n/a n/a (RC,mainClk0)
sramwe n/a n/a (RC,mainClk0)
sramAD<18> n/a n/a (RC,mainClk0)
sramAD<17> n/a n/a (RC,mainClk0)
sramAD<16> n/a n/a (RC,mainClk0)
sramAD<15> n/a n/a (RC,mainClk0)
sramAD<14> n/a n/a (RC,mainClk0)
sramAD<13> n/a n/a (RC,mainClk0)
sramAD<12> n/a n/a (RC,mainClk0)
sramAD<11> n/a n/a (RC,mainClk0)
sramAD<10> n/a n/a (RC,mainClk0)
sramAD<9> n/a n/a (RC,mainClk0)
sramAD<8> n/a n/a (RC,mainClk0)
sramAD<7> n/a n/a (RC,mainClk0)
sramAD<6> n/a n/a (RC,mainClk0)
sramAD<5> n/a n/a (RC,mainClk0)
sramAD<4> n/a n/a (RC,mainClk0)
sramAD<3> n/a n/a (RC,mainClk0)
sramAD<2> n/a n/a (RC,mainClk0)
sramAD<1> n/a n/a (RC,mainClk0)
sramAD<0> n/a n/a (RC,mainClk0)
sramDT<7> n/a n/a (RC,mainClk0)
sramDT<7> n/a n/a (RC,mainClk0)
sramDT<7> n/a n/a (RC,mainClk0)
sramDT<7> n/a n/a (RC,mainClk0)
sramDT<6> n/a n/a (RC,mainClk0)
sramDT<6> n/a n/a (RC,mainClk0)
sramDT<6> n/a n/a (RC,mainClk0)
sramDT<6> n/a n/a (RC,mainClk0)
sramDT<5> n/a n/a (RC,mainClk0)
sramDT<5> n/a n/a (RC,mainClk0)
sramDT<5> n/a n/a (RC,mainClk0)
sramDT<5> n/a n/a (RC,mainClk0)
sramDT<4> n/a n/a (RC,mainClk0)
sramDT<4> n/a n/a (RC,mainClk0)
sramDT<4> n/a n/a (RC,mainClk0)
sramDT<4> n/a n/a (RC,mainClk0)
sramDT<3> n/a n/a (RC,mainClk0)
sramDT<3> n/a n/a (RC,mainClk0)
sramDT<3> n/a n/a (RC,mainClk0)
sramDT<3> n/a n/a (RC,mainClk0)
sramDT<2> n/a n/a (RC,mainClk0)
sramDT<2> n/a n/a (RC,mainClk0)
sramDT<2> n/a n/a (RC,mainClk0)
sramDT<2> n/a n/a (RC,mainClk0)
sramDT<1> n/a n/a (RC,mainClk0)
sramDT<1> n/a n/a (RC,mainClk0)
sramDT<1> n/a n/a (RC,mainClk0)
sramDT<1> n/a n/a (RC,mainClk0)
sramDT<0> n/a n/a (RC,mainClk0)
sramDT<0> n/a n/a (RC,mainClk0)
sramDT<0> n/a n/a (RC,mainClk0)
sramDT<0> n/a n/a (RC,mainClk0)
Critical Path Timing:
---------------------
Arrival Required
Cell Time Time Fanout
Type (ns) (ns) Count Pin-Name
.........................................................
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