xilinxu.xnf

TOSHIBA公司的射频卡VERILOGHDL代码 包括TOP 顶层文件

PIN, I1, I, mainu_clockdivu_c106_c1_c0_n7, , , INV
PIN, O, O, mainU_clockdivU_C107_N12, , , INV
END
SYM, FMAP_22, FMAP, HU_SET=dec_rpl_32_174_9, LIBVER=2.0.0, RLOC=R0C0.F
PIN, I1, I, mainU_clockdivU_c<1>, , 
PIN, I2, I, mainU_clockdivU_a95, , 
PIN, I3, I, mainU_clockdivU_C106_N2, , 
PIN, I4, I, mainU_clockdivU_C2_N11, , 
PIN, O, I, mainU_clockdivU_C107_N12, , 
END
SYM, mainu_clockdivu_c106_c1_c1_c0, XOR, LIBVER=2.0.0
PIN, I0, I, mainU_clockdivU_C106_C1_cout0_net, , 
PIN, I1, I, mainU_clockdivU_c<2>, , 
PIN, O, O, mainu_clockdivu_c106_c1_c1_n3, , 
END
SYM, mainu_clockdivu_c106_c1_c1_c2, AND, LIBVER=2.0.0
PIN, I0, I, mainu_clockdivu_c106_c1_c1_n6, , , INV
PIN, I1, I, mainu_clockdivu_c106_c1_c1_n7, , , INV
PIN, O, O, mainU_clockdivU_C107_N18, , , INV
END
SYM, mainu_clockdivu_c106_c1_c1_c3, AND, LIBVER=2.0.0
PIN, I0, I, mainu_clockdivu_c106_c1_c1_n3, , , INV
PIN, I1, I, mainU_clockdivU_a95, , 
PIN, O, O, mainu_clockdivu_c106_c1_c1_n6, , 
END
SYM, mainu_clockdivu_c106_c1_c1_c4, AND, LIBVER=2.0.0
PIN, I0, I, mainU_clockdivU_C2_N11, , 
PIN, I1, I, mainU_clockdivU_a95, , , INV
PIN, O, O, mainu_clockdivu_c106_c1_c1_n7, , 
END
SYM, FMAP_23, FMAP, HU_SET=dec_rpl_32_174_9, LIBVER=2.0.0, RLOC=R0C0.G
PIN, I1, I, mainU_clockdivU_a95, , 
PIN, I2, I, mainU_clockdivU_C106_C1_cout0_net, , 
PIN, I3, I, mainU_clockdivU_C2_N11, , 
PIN, I4, I, mainU_clockdivU_c<2>, , 
PIN, O, I, mainU_clockdivU_C107_N18, , 
END
SYM, mainU_clockdivU_C106_C1_C2, CY4, HU_SET=dec_rpl_32_174_9, LIBVER=2.0.0, RLOC=R0C0
PIN, COUT, O, mainU_clockdivU_C106_N7, , 
PIN, COUT0, O, mainU_clockdivU_C106_C1_cout0_net, , 
PIN, CIN, I, mainU_clockdivU_C106_N2, , 
PIN, A0, I, mainU_clockdivU_c<1>, , 
PIN, A1, I, mainU_clockdivU_c<2>, , 
PIN, C0, I, mainU_clockdivU_C106_C1_N0, , 
PIN, C1, I, mainU_clockdivU_C106_C1_N1, , 
PIN, C2, I, mainU_clockdivU_C106_C1_N2, , 
PIN, C3, I, mainU_clockdivU_C106_C1_N3, , 
PIN, C4, I, mainU_clockdivU_C106_C1_N4, , 
PIN, C5, I, mainU_clockdivU_C106_C1_N5, , 
PIN, C6, I, mainU_clockdivU_C106_C1_N6, , 
PIN, C7, I, mainU_clockdivU_C106_C1_N7, , 
END
SYM, mainU_clockdivU_C106_C1_C3, CY4_25, CYMODE=DEC-FG-CI, LIBVER=2.0.0
PIN, C7, O, mainU_clockdivU_C106_C1_N7, , 
PIN, C6, O, mainU_clockdivU_C106_C1_N6, , 
PIN, C5, O, mainU_clockdivU_C106_C1_N5, , 
PIN, C4, O, mainU_clockdivU_C106_C1_N4, , 
PIN, C3, O, mainU_clockdivU_C106_C1_N3, , 
PIN, C2, O, mainU_clockdivU_C106_C1_N2, , 
PIN, C1, O, mainU_clockdivU_C106_C1_N1, , 
PIN, C0, O, mainU_clockdivU_C106_C1_N0, , 
END
SYM, mainu_clockdivu_c106_c2_c0_c0, XOR, LIBVER=2.0.0
PIN, I0, I, mainU_clockdivU_c<3>, , 
PIN, I1, I, mainU_clockdivU_C106_N7, , 
PIN, O, O, mainu_clockdivu_c106_c2_c0_n3, , 
END
SYM, mainu_clockdivu_c106_c2_c0_c2, AND, LIBVER=2.0.0
PIN, I0, I, mainu_clockdivu_c106_c2_c0_n3, , , INV
PIN, I1, I, mainU_clockdivU_a95, , 
PIN, O, O, mainu_clockdivu_c106_c2_c0_n5, , 
END
SYM, mainu_clockdivu_c106_c2_c0_c3, AND, LIBVER=2.0.0
PIN, I0, I, mainU_clockdivU_C2_N11, , 
PIN, I1, I, mainU_clockdivU_a95, , , INV
PIN, O, O, mainu_clockdivu_c106_c2_c0_n7, , 
END
SYM, mainu_clockdivu_c106_c2_c0_c4, AND, LIBVER=2.0.0
PIN, I0, I, mainu_clockdivu_c106_c2_c0_n5, , , INV
PIN, I1, I, mainu_clockdivu_c106_c2_c0_n7, , , INV
PIN, O, O, mainU_clockdivU_C107_N24, , , INV
END
SYM, FMAP_24, FMAP, HU_SET=dec_rpl_32_174_10, LIBVER=2.0.0, RLOC=R0C0.F
PIN, I1, I, mainU_clockdivU_c<3>, , 
PIN, I2, I, mainU_clockdivU_a95, , 
PIN, I3, I, mainU_clockdivU_C106_N7, , 
PIN, I4, I, mainU_clockdivU_C2_N11, , 
PIN, O, I, mainU_clockdivU_C107_N24, , 
END
SYM, mainu_clockdivu_c106_c2_c1_c0, XOR, LIBVER=2.0.0
PIN, I0, I, mainU_clockdivU_C106_C2_cout0_net, , 
PIN, I1, I, mainU_clockdivU_c<4>, , 
PIN, O, O, mainu_clockdivu_c106_c2_c1_n3, , 
END
SYM, mainu_clockdivu_c106_c2_c1_c2, AND, LIBVER=2.0.0
PIN, I0, I, mainu_clockdivu_c106_c2_c1_n3, , , INV
PIN, I1, I, mainU_clockdivU_a95, , 
PIN, O, O, mainu_clockdivu_c106_c2_c1_n5, , 
END
SYM, mainu_clockdivu_c106_c2_c1_c3, AND, LIBVER=2.0.0
PIN, I0, I, mainU_clockdivU_C2_N11, , 
PIN, I1, I, mainU_clockdivU_a95, , , INV
PIN, O, O, mainu_clockdivu_c106_c2_c1_n7, , 
END
SYM, mainu_clockdivu_c106_c2_c1_c4, AND, LIBVER=2.0.0
PIN, I0, I, mainu_clockdivu_c106_c2_c1_n5, , , INV
PIN, I1, I, mainu_clockdivu_c106_c2_c1_n7, , , INV
PIN, O, O, mainU_clockdivU_C107_N30, , , INV
END
SYM, FMAP_25, FMAP, HU_SET=dec_rpl_32_174_10, LIBVER=2.0.0, RLOC=R0C0.G
PIN, I1, I, mainU_clockdivU_a95, , 
PIN, I2, I, mainU_clockdivU_C106_C2_cout0_net, , 
PIN, I3, I, mainU_clockdivU_C2_N11, , 
PIN, I4, I, mainU_clockdivU_c<4>, , 
PIN, O, I, mainU_clockdivU_C107_N30, , 
END
SYM, mainU_clockdivU_C106_C2_C2, CY4, HU_SET=dec_rpl_32_174_10, LIBVER=2.0.0, RLOC=R0C0
PIN, COUT, O, mainU_clockdivU_C106_N12, , 
PIN, COUT0, O, mainU_clockdivU_C106_C2_cout0_net, , 
PIN, CIN, I, mainU_clockdivU_C106_N7, , 
PIN, A0, I, mainU_clockdivU_c<3>, , 
PIN, A1, I, mainU_clockdivU_c<4>, , 
PIN, C0, I, mainU_clockdivU_C106_C2_N0, , 
PIN, C1, I, mainU_clockdivU_C106_C2_N1, , 
PIN, C2, I, mainU_clockdivU_C106_C2_N2, , 
PIN, C3, I, mainU_clockdivU_C106_C2_N3, , 
PIN, C4, I, mainU_clockdivU_C106_C2_N4, , 
PIN, C5, I, mainU_clockdivU_C106_C2_N5, , 
PIN, C6, I, mainU_clockdivU_C106_C2_N6, , 
PIN, C7, I, mainU_clockdivU_C106_C2_N7, , 
END
SYM, mainU_clockdivU_C106_C2_C3, CY4_25, CYMODE=DEC-FG-CI, LIBVER=2.0.0
PIN, C7, O, mainU_clockdivU_C106_C2_N7, , 
PIN, C6, O, mainU_clockdivU_C106_C2_N6, , 
PIN, C5, O, mainU_clockdivU_C106_C2_N5, , 
PIN, C4, O, mainU_clockdivU_C106_C2_N4, , 
PIN, C3, O, mainU_clockdivU_C106_C2_N3, , 
PIN, C2, O, mainU_clockdivU_C106_C2_N2, , 
PIN, C1, O, mainU_clockdivU_C106_C2_N1, , 
PIN, C0, O, mainU_clockdivU_C106_C2_N0, , 
END
SYM, mainu_clockdivu_c106_c3_c0_c0, XOR, LIBVER=2.0.0
PIN, I0, I, mainU_clockdivU_c<5>, , 
PIN, I1, I, mainU_clockdivU_C106_N12, , 
PIN, O, O, mainu_clockdivu_c106_c3_c0_n3, , 
END
SYM, mainu_clockdivu_c106_c3_c0_c2, AND, LIBVER=2.0.0
PIN, I0, I, mainu_clockdivu_c106_c3_c0_n3, , , INV
PIN, I1, I, mainU_clockdivU_a95, , 
PIN, O, O, mainu_clockdivu_c106_c3_c0_n5, , 
END
SYM, mainu_clockdivu_c106_c3_c0_c3, AND, LIBVER=2.0.0
PIN, I0, I, mainU_clockdivU_C2_N11, , 
PIN, I1, I, mainU_clockdivU_a95, , , INV
PIN, O, O, mainu_clockdivu_c106_c3_c0_n7, , 
END
SYM, mainu_clockdivu_c106_c3_c0_c4, AND, LIBVER=2.0.0
PIN, I0, I, mainu_clockdivu_c106_c3_c0_n5, , , INV
PIN, I1, I, mainu_clockdivu_c106_c3_c0_n7, , , INV
PIN, O, O, mainU_clockdivU_C107_N36, , , INV
END
SYM, FMAP_26, FMAP, HU_SET=dec_rpl_32_174_11, LIBVER=2.0.0, RLOC=R0C0.F
PIN, I1, I, mainU_clockdivU_c<5>, , 
PIN, I2, I, mainU_clockdivU_a95, , 
PIN, I3, I, mainU_clockdivU_C106_N12, , 
PIN, I4, I, mainU_clockdivU_C2_N11, , 
PIN, O, I, mainU_clockdivU_C107_N36, , 
END
SYM, mainu_clockdivu_c106_c3_c1_c0, XOR, LIBVER=2.0.0
PIN, I0, I, mainU_clockdivU_C106_C3_cout0_net, , 
PIN, I1, I, mainU_clockdivU_c<6>, , 
PIN, O, O, mainu_clockdivu_c106_c3_c1_n3, , 
END
SYM, mainu_clockdivu_c106_c3_c1_c2, AND, LIBVER=2.0.0
PIN, I0, I, mainu_clockdivu_c106_c3_c1_n3, , , INV
PIN, I1, I, mainU_clockdivU_a95, , 
PIN, O, O, mainu_clockdivu_c106_c3_c1_n5, , 
END
SYM, mainu_clockdivu_c106_c3_c1_c3, AND, LIBVER=2.0.0
PIN, I0, I, mainU_clockdivU_C2_N35, , 
PIN, I1, I, mainU_clockdivU_a95, , , INV
PIN, O, O, mainu_clockdivu_c106_c3_c1_n7, , 
END
SYM, mainu_clockdivu_c106_c3_c1_c4, AND, LIBVER=2.0.0
PIN, I0, I, mainu_clockdivu_c106_c3_c1_n5, , , INV
PIN, I1, I, mainu_clockdivu_c106_c3_c1_n7, , , INV
PIN, O, O, mainU_clockdivU_C107_N42, , , INV
END
SYM, FMAP_27, FMAP, HU_SET=dec_rpl_32_174_11, LIBVER=2.0.0, RLOC=R0C0.G
PIN, I1, I, mainU_clockdivU_a95, , 
PIN, I2, I, mainU_clockdivU_C106_C3_cout0_net, , 
PIN, I3, I, mainU_clockdivU_C2_N35, , 
PIN, I4, I, mainU_clockdivU_c<6>, , 
PIN, O, I, mainU_clockdivU_C107_N42, , 
END
SYM, mainU_clockdivU_C106_C3_C2, CY4, HU_SET=dec_rpl_32_174_11, LIBVER=2.0.0, RLOC=R0C0
PIN, COUT0, O, mainU_clockdivU_C106_C3_cout0_net, , 
PIN, CIN, I, mainU_clockdivU_C106_N12, , 
PIN, A0, I, mainU_clockdivU_c<5>, , 
PIN, A1, I, mainU_clockdivU_c<6>, , 
PIN, C0, I, mainU_clockdivU_C106_C3_N0, , 
PIN, C1, I, mainU_clockdivU_C106_C3_N1, , 
PIN, C2, I, mainU_clockdivU_C106_C3_N2, , 
PIN, C3, I, mainU_clockdivU_C106_C3_N3, , 
PIN, C4, I, mainU_clockdivU_C106_C3_N4, , 
PIN, C5, I, mainU_clockdivU_C106_C3_N5, , 
PIN, C6, I, N502, , 
PIN, C7, I, mainU_clockdivU_C106_C3_N7, , 
END
SYM, mainU_clockdivU_C106_C3_C3, CY4_25, CYMODE=DEC-FG-CI, LIBVER=2.0.0
PIN, C7, O, mainU_clockdivU_C106_C3_N7, , 
PIN, C6, O, N502, , 
PIN, C5, O, mainU_clockdivU_C106_C3_N5, , 
PIN, C4, O, mainU_clockdivU_C106_C3_N4, , 
PIN, C3, O, mainU_clockdivU_C106_C3_N3, , 
PIN, C2, O, mainU_clockdivU_C106_C3_N2, , 
PIN, C1, O, mainU_clockdivU_C106_C3_N1, , 
PIN, C0, O, mainU_clockdivU_C106_C3_N0, , 
END
SYM, EEPEmu0_RB_reg, DFF, INIT=S, LIBVER=2.0.0
PIN, D, I, EEPEmu0_stat<1>, , 
PIN, C, I, N483_BUFGed, , 
PIN, PRE, I, N377, , 
PIN, CE, I, EEPEmu0_C30_N9, , 
PIN, Q, O, RB, , 
END
SYM, EEPEmu0_sramwe_reg, DFF, INIT=S, LIBVER=2.0.0
PIN, D, I, EEPEmu0_stat<3>, , 
PIN, C, I, N483_BUFGed, , 
PIN, PRE, I, N377, , 
PIN, CE, I, EEPEmu0_N165, , 
PIN, Q, O, N_sramwe, , 
END
SYM, EEPEmu0_ER12_reg, DFF, LIBVER=2.0.0
PIN, D, I, ER1, , 
PIN, C, I, N484_BUFGed, , , INV
PIN, Q, O, EEPEmu0_ER12, , 
END
SYM, EEPEmu0_WR02_reg, DFF, LIBVER=2.0.0
PIN, D, I, WR0, , 
PIN, C, I, N484_BUFGed, , , INV
PIN, Q, O, EEPEmu0_WR02, , 
END
SYM, EEPEmu0_wbuf02sramDT_reg, DFF, LIBVER=2.0.0
PIN, D, I, N471, , 
PIN, C, I, N483_BUFGed, , 
PIN, CLR, I, N377, , 
PIN, CE, I, EEPEmu0_C34_N9, , 
PIN, Q, O, EEPEmu0_wbuf02sramDT, , 
END
SYM, EEPEmu0_sramDT2D_reg, DFF, LIBVER=2.0.0
PIN, D, I, N471, , 
PIN, C, I, N483_BUFGed, , 
PIN, CLR, I, N377, , 
PIN, CE, I, EEPEmu0_C21_N9, , 
PIN, Q, O, EEPEmu0_sramDT2D, , 
END
SYM, EEPEmu0_sramcs_reg, LD_1, FILE=./ld_1.xnf, LIBVER=2.0.0
PIN, Q, O, N_sramcs, , 
PIN, D, I, N334, , 
PIN, G, I, breset, , 
END
SYM, EEPEmu0_sramoe_reg, DFF, INIT=S, LIBVER=2.0.0
PIN, D, I, N471, , 
PIN, C, I, N483_BUFGed, , 
PIN, PRE, I, N377, , 
PIN, CE, I, N425, , 
PIN, Q, O, N_sramoe, , 
END
SYM, EEPEmu0_wbuf0_reg<0>, DFF, LIBVER=2.0.0
PIN, D, I, EEPEmu0_C31_N6, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C17_N5, , 
PIN, Q, O, EEPEmu0_wbuf0<0>, , 
END
SYM, EEPEmu0_wbuf0_reg<1>, DFF, LIBVER=2.0.0
PIN, D, I, EEPEmu0_C31_N12, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C17_N5, , 
PIN, Q, O, EEPEmu0_wbuf0<1>, , 
END
SYM, EEPEmu0_wbuf0_reg<2>, DFF, LIBVER=2.0.0
PIN, D, I, EEPEmu0_C31_N18, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C17_N5, , 
PIN, Q, O, EEPEmu0_wbuf0<2>, , 
END
SYM, EEPEmu0_wbuf0_reg<3>, DFF, LIBVER=2.0.0
PIN, D, I, EEPEmu0_C31_N24, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C17_N5, , 
PIN, Q, O, EEPEmu0_wbuf0<3>, , 
END
SYM, EEPEmu0_wbuf0_reg<4>, DFF, LIBVER=2.0.0
PIN, D, I, EEPEmu0_C31_N30, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C17_N5, , 
PIN, Q, O, EEPEmu0_wbuf0<4>, , 
END
SYM, EEPEmu0_wbuf0_reg<5>, DFF, LIBVER=2.0.0
PIN, D, I, EEPEmu0_C31_N36, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C17_N5, , 
PIN, Q, O, EEPEmu0_wbuf0<5>, , 
END
SYM, EEPEmu0_wbuf0_reg<6>, DFF, LIBVER=2.0.0
PIN, D, I, EEPEmu0_C31_N42, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C17_N5, , 
PIN, Q, O, EEPEmu0_wbuf0<6>, , 
END
SYM, EEPEmu0_wbuf0_reg<7>, DFF, LIBVER=2.0.0
PIN, D, I, EEPEmu0_C31_N48, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C17_N5, , 
PIN, Q, O, EEPEmu0_wbuf0<7>, , 
END
SYM, EEPEmu0_cnt_reg<0>, DFF, HU_SET=inc_rpl_14_168_0, LIBVER=2.0.0, RLOC=R0C0.FFY
PIN, D, I, EEPEmu0_C27_N5, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C16_N5, , 
PIN, Q, O, EEPEmu0_cnt<0>, , 
END
SYM, EEPEmu0_cnt_reg<1>, DFF, HU_SET=inc_rpl_14_168_1, LIBVER=2.0.0, RLOC=R0C0.FFX
PIN, D, I, EEPEmu0_C27_N10, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C16_N5, , 
PIN, Q, O, EEPEmu0_cnt<1>, , 
END
SYM, EEPEmu0_cnt_reg<2>, DFF, HU_SET=inc_rpl_14_168_1, LIBVER=2.0.0, RLOC=R0C0.FFY
PIN, D, I, EEPEmu0_C27_N15, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C16_N5, , 
PIN, Q, O, EEPEmu0_cnt<2>, , 
END
SYM, EEPEmu0_cnt_reg<3>, DFF, HU_SET=inc_rpl_14_168_2, LIBVER=2.0.0, RLOC=R0C0.FFX
PIN, D, I, EEPEmu0_C27_N20, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C16_N5, , 
PIN, Q, O, EEPEmu0_cnt<3>, , 
END
SYM, EEPEmu0_cnt_reg<4>, DFF, HU_SET=inc_rpl_14_168_2, LIBVER=2.0.0, RLOC=R0C0.FFY
PIN, D, I, EEPEmu0_C27_N25, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C16_N5, , 
PIN, Q, O, EEPEmu0_cnt<4>, , 
END
SYM, EEPEmu0_cnt_reg<5>, DFF, HU_SET=inc_rpl_14_168_3, LIBVER=2.0.0, RLOC=R0C0.FFX
PIN, D, I, EEPEmu0_C27_N30, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C16_N5, , 
PIN, Q, O, EEPEmu0_cnt<5>, , 
END
SYM, EEPEmu0_cnt_reg<6>, DFF, HU_SET=inc_rpl_14_168_3, LIBVER=2.0.0, RLOC=R0C0.FFY
PIN, D, I, EEPEmu0_C27_N35, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C16_N5, , 
PIN, Q, O, EEPEmu0_cnt<6>, , 
END
SYM, EEPEmu0_cnt_reg<7>, DFF, HU_SET=inc_rpl_14_168_4, LIBVER=2.0.0, RLOC=R0C0.FFX
PIN, D, I, EEPEmu0_C27_N40, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C16_N5, , 
PIN, Q, O, EEPEmu0_cnt<7>, , 
END
SYM, EEPEmu0_cnt_reg<8>, DFF, HU_SET=inc_rpl_14_168_4, LIBVER=2.0.0, RLOC=R0C0.FFY
PIN, D, I, EEPEmu0_C27_N45, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C16_N5, , 
PIN, Q, O, EEPEmu0_cnt<8>, , 
END
SYM, EEPEmu0_cnt_reg<9>, DFF, HU_SET=inc_rpl_14_168_5, LIBVER=2.0.0, RLOC=R0C0.FFX
PIN, D, I, EEPEmu0_C27_N50, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C16_N5, , 
PIN, Q, O, EEPEmu0_cnt<9>, , 
END
SYM, EEPEmu0_cnt_reg<10>, DFF, HU_SET=inc_rpl_14_168_5, LIBVER=2.0.0, RLOC=R0C0.FFY
PIN, D, I, EEPEmu0_C27_N55, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C16_N5, , 
PIN, Q, O, EEPEmu0_cnt<10>, , 
END
SYM, EEPEmu0_cnt_reg<11>, DFF, HU_SET=inc_rpl_14_168_6, LIBVER=2.0.0, RLOC=R0C0.FFX
PIN, D, I, EEPEmu0_C27_N60, , 
PIN, C, I, N483_BUFGed, , 
PIN, CE, I, EEPEmu0_C16_N5, , 
PIN, Q, O, EEPEmu0_cnt<11>, ,