t6n76_3.twr

TOSHIBA公司的射频卡VERILOGHDL代码 包括TOP 顶层文件

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Xilinx TRACE, Version C.22
Copyright (c) 1995-1999 Xilinx, Inc.  All rights reserved.

Design file:              t6n76_3.ncd
Physical constraint file: t6n76_3.pcf
Device,speed:             xc4085xl,-1 (C 1.1.2.2 FINAL)
Report level:             error report
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WARNING:Timing:181 - No timing constraints found, doing default enumeration.

================================================================================
Timing constraint: Default period analysis
 18197 items analyzed, 0 timing errors detected.
 Minimum period is  94.630ns.
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================================================================================
Timing constraint: Default net enumeration
 854 items analyzed, 0 timing errors detected.
 Maximum net delay is  28.664ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock rfClk0
---------------+------------+------------+
               |  Setup to  |  Hold to   |
Source Pad     | clk (edge) | clk (edge) |
---------------+------------+------------+
rfData         |   16.564(R)|    0.000(R)|
---------------+------------+------------+

Clock rfClk0 to Pad
---------------+------------+
               | clk (edge) |
Destination Pad|   to PAD   |
---------------+------------+
rfOut          |   34.539(R)|
---------------+------------+

Clock to Setup on destination clock rfClk0
---------------+---------+---------+---------+---------+
               | Src/Dest| Src/Dest| Src/Dest| Src/Dest|
Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|
---------------+---------+---------+---------+---------+
rfClk0         |   39.443|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 18197 paths, 854 nets, and 3529 connections (100.0% coverage)

Design statistics:
   Minimum period:  94.630ns (Maximum frequency:  10.567MHz)
   Maximum net delay:  28.664ns

WARNING:Timing:33 - Clock nets using non-dedicated resources were found in this
   design. Clock skew on these resources will not be automatically addressed
   during path analysis. To create a timing report that analyzes clock skew for
   these paths, run trce with the '-skew' option.

Analysis completed FRI 11 AUG 13:25:45 2000--------------------------------------------------------------------------------