t6n76_3.bld

来自「TOSHIBA公司的射频卡VERILOGHDL代码 包括TOP 顶层文件」· BLD 代码 · 共 37 行

ngdbuild:  version C.22
Copyright (c) 1995-1999 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -p xc4085xl-1-bg432 -uc t6n76_3.ucf -dd ..
c:\prj\verilog\try\ticket2\c\t6n76_3\t6n76_3.xnf t6n76_3.ngd 

Launcher: Executing xnf2ngd -p xc4000xl -u
"c:\prj\verilog\try\ticket2\c\t6n76_3\t6n76_3.xnf"
"C:\prj\Verilog\Try\Ticket2\c\T6N76_3\xproj\ver10\t6n76_3.ngo"
xnf2ngd:  version C.22
Copyright (c) 1995-1999 Xilinx, Inc.  All rights reserved.
   using XNF gate model
   reading XNF file "c:/prj/verilog/try/ticket2/c/t6n76_3/t6n76_3.xnf" ...
   Writing NGO file
"C:/prj/Verilog/Try/Ticket2/c/T6N76_3/xproj/ver10/t6n76_3.ngo" ...
Reading NGO file "C:/prj/Verilog/Try/Ticket2/c/T6N76_3/xproj/ver10/t6n76_3.ngo"
...
Reading component libraries for design expansion...

Annotating constraints to design from file "t6n76_3.ucf" ...

Checking timing specifications ...

Checking expanded design ...
WARNING:NgdHelpers:357 - clock net "breset" has non-clock connections
WARNING:NgdHelpers:357 - clock net "mainU_mainClk1" has non-clock connections
WARNING:NgdHelpers:357 - clock net "N483_BUFGed" has non-clock connections
WARNING:NgdHelpers:357 - clock net "N484_BUFGed" has non-clock connections

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   4

Writing NGD file "t6n76_3.ngd" ...

Writing NGDBUILD log file "t6n76_3.bld"...