mainu.out

TOSHIBA公司的射频卡VERILOGHDL代码 包括TOP 顶层文件

Reading in the Synopsys verilog primitives.

Statistics for case statements in always block at line 233 in file
        'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           235            |    user/auto     |
|           253            |    user/auto     |
|           271            |    user/auto     |
===============================================

Statistics for case statements in always block at line 347 in file
        'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|           372            |    user/auto     |
|           380            |    auto/auto     |
|           403            |    auto/auto     |
|           607            |     no/auto      |
|           609            |    auto/auto     |
|           630            |    auto/auto     |
===============================================

Inferred memory devices in process 
	in routine MainU line 96 in file
         'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      tmd0_reg       | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | Y  |
===============================================================================

tmd0_reg
--------
    Async-reset: TST0'
    Sync-toggle: true



Inferred memory devices in process 
	in routine MainU line 97 in file
         'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      tmd1_reg       | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | Y  |
===============================================================================

tmd1_reg
--------
    Async-reset: TST0'
    Sync-toggle: true



Inferred memory devices in process 
	in routine MainU line 98 in file
         'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      tmd2_reg       | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | Y  |
===============================================================================

tmd2_reg
--------
    Async-reset: TST0'
    Sync-toggle: true



Inferred memory devices in process 
	in routine MainU line 99 in file
         'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      tmd3_reg       | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | Y  |
===============================================================================

tmd3_reg
--------
    Async-reset: TST0'
    Sync-toggle: true



Inferred THREE-STATE control devices in process 
	in routine MainU line 112 in
         file 'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'.
============================================================================
|     Three-state Device Name      |               Type               | MB |
============================================================================
|             ORD_tri              |        Three-state Buffer        | N  |
============================================================================


Inferred THREE-STATE control devices in process 
	in routine MainU line 116 in
         file 'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'.
============================================================================
|     Three-state Device Name      |               Type               | MB |
============================================================================
|             IWD_tri              |        Three-state Buffer        | N  |
============================================================================


Inferred THREE-STATE control devices in process 
	in routine MainU line 166 in
         file 'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'.
============================================================================
|     Three-state Device Name      |               Type               | MB |
============================================================================
|             D_tri<4>             |        Three-state Buffer        | N  |
|             D_tri<0>             |        Three-state Buffer        | N  |
|             D_tri<2>             |        Three-state Buffer        | N  |
|             D_tri<6>             |        Three-state Buffer        | N  |
|             D_tri<7>             |        Three-state Buffer        | N  |
|             D_tri<3>             |        Three-state Buffer        | N  |
|             D_tri<1>             |        Three-state Buffer        | N  |
|             D_tri<5>             |        Three-state Buffer        | N  |
============================================================================


Inferred memory devices in process 
	in routine MainU line 185 in file
         'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       BCE_reg       | Flip-flop |   1   |  -  | -  | N  | Y  | N  | N  | N  |
|      BDIS_reg       | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | N  |
|       BOE_reg       | Flip-flop |   1   |  -  | -  | N  | Y  | N  | N  | N  |
|       BWE_reg       | Flip-flop |   1   |  -  | -  | N  | Y  | N  | N  | N  |
|       ER1_reg       | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | N  |
|       WR0_reg       | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | N  |
===============================================================================

BCE_reg
-------
    Async-set: breset'


BDIS_reg
--------
    Async-reset: breset'


BOE_reg
-------
    Async-set: breset'


BWE_reg
-------
    Async-set: breset'


ER1_reg
-------
    Async-reset: breset'


WR0_reg
-------
    Async-reset: breset'



Inferred memory devices in process 
	in routine MainU line 189 in file
         'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       RB2_reg       | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
===============================================================================

RB2_reg
-------
    set/reset/toggle: none



Inferred memory devices in process 
	in routine MainU line 213 in file
         'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     tpwclk0_reg     | Flip-flop |   2   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================

tpwclk0_reg (width 2)
---------------------
    Async-reset: breset'



Inferred memory devices in process 
	in routine MainU line 298 in file
         'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      rfOut_reg      | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | N  |
===============================================================================

rfOut_reg
---------
    Async-reset: breset'



Inferred memory devices in process 
	in routine MainU line 338 in file
         'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      phase_reg      | Flip-flop |   3   |  Y  | N  | N  | N  | Y  | N  | N  |
===============================================================================

phase_reg (width 3)
-------------------
    Sync-reset: SRst



Inferred memory devices in process 
	in routine MainU line 347 in file
         'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      bnum_reg       | Flip-flop |   5   |  Y  | N  | Y  | N  | N  | N  | N  |
|    idmerror_reg     | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
|   idmwritable_reg   | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | N  |
|     operate_reg     | Flip-flop |   4   |  N  | N  | ?  | ?  | ?  | ?  | ?  |
|    polllock_reg     | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | N  |
|     rcvbuf_reg      | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
|      recv_reg       | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | N  |
|     sndexec_reg     | Flip-flop |   1   |  -  | -  | Y  | N  | N  | N  | N  |
|      stat_reg       | Flip-flop |   7   |  N  | N  | ?  | ?  | ?  | ?  | ?  |
===============================================================================

bnum_reg (width 5)
------------------
    Async-reset: breset'


idmerror_reg
------------
    set/reset/toggle: none


idmwritable_reg
---------------
    Async-reset: breset'


operate_reg<0>
--------------
    Async-reset: breset'
    Sync-toggle: n2393' n_1737 phase<0> phase<1> phase<2>' stat<6>'


operate_reg<2>
--------------
    Async-reset: breset'


operate_reg<3>
--------------
    Async-reset: breset'


operate_reg<1>
--------------
    Async-reset: breset'


polllock_reg
------------
    Async-reset: breset'


rcvbuf_reg (width 8)
--------------------
    set/reset/toggle: none


recv_reg
--------
    Async-reset: breset'


sndexec_reg
-----------
    Async-reset: breset'


stat_reg<5>
-----------
    Async-reset: breset'


stat_reg<1>
-----------
    Async-reset: breset'


stat_reg<3>
-----------
    Async-reset: breset'


stat_reg<6>
-----------
    Async-reset: breset'


stat_reg<2>
-----------
    Async-reset: breset'


stat_reg<0>
-----------
    Async-reset: breset'


stat_reg<4>
-----------
    Async-reset: breset'


Writing to hnl file 'c:\prj\Verilog\Try\Ticket2\c\T6N76_3\t6n76_3/workdirs/WORK/MainU.hnl'
Warning: You are using the full_case directive  with a case statement in which not all cases are covered.  (HDL-370)
Warning: You are using the full_case directive  with a case statement in which not all cases are covered.  (HDL-370)
Warning: You are using the full_case directive  with a case statement in which not all cases are covered.  (HDL-370)
Warning: Variable 'operate' is being read 
	in routine MainU line 233 in file 'C:/prj/verilog/try/ticket2/c/t6n76_3/mainx.v',
	but does not occur in the timing control of the block which begins
	there.   (HDL-180)
Warning: You are using the full_case directive  with a case statement in which not all cases are covered.  (HDL-370)