szz_map.vhd

来自「VHDL设计的数字时钟」· VHDL 代码 · 共 2,022 行 · 第 1/5 页

    )
    port map (
      I => a_0_BXINVNOT,
      O => a_0_CYINIT
    );
  a_0_CYSELF_4 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_N3725,
      O => a_0_CYSELF
    );
  a_0_BXINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => a_0_BXINVNOT
    );
  a_0_DYMUX_5 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_0_XORG,
      O => a_0_DYMUX
    );
  a_0_XORG_6 : X_XOR2
    port map (
      I0 => a_LPM_COUNTER_1_n0000_0_cyo,
      I1 => a_0_G,
      O => a_0_XORG
    );
  a_0_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_0_CYMUXG,
      O => a_LPM_COUNTER_1_n0000_1_cyo
    );
  a_0_CYMUXG_7 : X_MUX2
    port map (
      IA => a_0_LOGIC_ZERO,
      IB => a_LPM_COUNTER_1_n0000_0_cyo,
      SEL => a_0_CYSELG,
      O => a_0_CYMUXG
    );
  a_0_CYSELG_8 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_0_G,
      O => a_0_CYSELG
    );
  a_0_SRINV_9 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0025,
      O => a_0_SRINV
    );
  a_0_CLKINV_10 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => inclk_BUFGP,
      O => a_0_CLKINV
    );
  a_2_LOGIC_ZERO_11 : X_ZERO
    port map (
      O => a_2_LOGIC_ZERO
    );
  a_2_DXMUX_12 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_2_XORF,
      O => a_2_DXMUX
    );
  a_2_XORF_13 : X_XOR2
    port map (
      I0 => a_2_CYINIT,
      I1 => a_2_F,
      O => a_2_XORF
    );
  a_2_CYMUXF : X_MUX2
    port map (
      IA => a_2_LOGIC_ZERO,
      IB => a_2_CYINIT,
      SEL => a_2_CYSELF,
      O => a_LPM_COUNTER_1_n0000_2_cyo
    );
  a_2_CYMUXF2_14 : X_MUX2
    port map (
      IA => a_2_LOGIC_ZERO,
      IB => a_2_LOGIC_ZERO,
      SEL => a_2_CYSELF,
      O => a_2_CYMUXF2
    );
  a_2_CYINIT_15 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_LPM_COUNTER_1_n0000_1_cyo,
      O => a_2_CYINIT
    );
  a_2_CYSELF_16 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_2_F,
      O => a_2_CYSELF
    );
  a_2_DYMUX_17 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_2_XORG,
      O => a_2_DYMUX
    );
  a_2_XORG_18 : X_XOR2
    port map (
      I0 => a_LPM_COUNTER_1_n0000_2_cyo,
      I1 => a_2_G,
      O => a_2_XORG
    );
  a_2_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_2_CYMUXFAST,
      O => a_LPM_COUNTER_1_n0000_3_cyo
    );
  a_2_FASTCARRY_19 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_LPM_COUNTER_1_n0000_1_cyo,
      O => a_2_FASTCARRY
    );
  a_2_CYAND_20 : X_AND2
    port map (
      I0 => a_2_CYSELG,
      I1 => a_2_CYSELF,
      O => a_2_CYAND
    );
  a_2_CYMUXFAST_21 : X_MUX2
    port map (
      IA => a_2_CYMUXG2,
      IB => a_2_FASTCARRY,
      SEL => a_2_CYAND,
      O => a_2_CYMUXFAST
    );
  a_2_CYMUXG2_22 : X_MUX2
    port map (
      IA => a_2_LOGIC_ZERO,
      IB => a_2_CYMUXF2,
      SEL => a_2_CYSELG,
      O => a_2_CYMUXG2
    );
  a_2_CYSELG_23 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_2_G,
      O => a_2_CYSELG
    );
  a_2_SRINV_24 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0025,
      O => a_2_SRINV
    );
  a_2_CLKINV_25 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => inclk_BUFGP,
      O => a_2_CLKINV
    );
  a_4_LOGIC_ZERO_26 : X_ZERO
    port map (
      O => a_4_LOGIC_ZERO
    );
  a_4_DXMUX_27 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_4_XORF,
      O => a_4_DXMUX
    );
  a_4_XORF_28 : X_XOR2
    port map (
      I0 => a_4_CYINIT,
      I1 => a_4_F,
      O => a_4_XORF
    );
  a_4_CYMUXF : X_MUX2
    port map (
      IA => a_4_LOGIC_ZERO,
      IB => a_4_CYINIT,
      SEL => a_4_CYSELF,
      O => a_LPM_COUNTER_1_n0000_4_cyo
    );
  a_4_CYMUXF2_29 : X_MUX2
    port map (
      IA => a_4_LOGIC_ZERO,
      IB => a_4_LOGIC_ZERO,
      SEL => a_4_CYSELF,
      O => a_4_CYMUXF2
    );
  a_4_CYINIT_30 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_LPM_COUNTER_1_n0000_3_cyo,
      O => a_4_CYINIT
    );
  a_4_CYSELF_31 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_4_F,
      O => a_4_CYSELF
    );
  a_4_DYMUX_32 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_4_XORG,
      O => a_4_DYMUX
    );
  a_4_XORG_33 : X_XOR2
    port map (
      I0 => a_LPM_COUNTER_1_n0000_4_cyo,
      I1 => a_4_G,
      O => a_4_XORG
    );
  a_4_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_4_CYMUXFAST,
      O => a_LPM_COUNTER_1_n0000_5_cyo
    );
  a_4_FASTCARRY_34 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_LPM_COUNTER_1_n0000_3_cyo,
      O => a_4_FASTCARRY
    );
  a_4_CYAND_35 : X_AND2
    port map (
      I0 => a_4_CYSELG,
      I1 => a_4_CYSELF,
      O => a_4_CYAND
    );
  a_4_CYMUXFAST_36 : X_MUX2
    port map (
      IA => a_4_CYMUXG2,
      IB => a_4_FASTCARRY,
      SEL => a_4_CYAND,
      O => a_4_CYMUXFAST
    );
  a_4_CYMUXG2_37 : X_MUX2
    port map (
      IA => a_4_LOGIC_ZERO,
      IB => a_4_CYMUXF2,
      SEL => a_4_CYSELG,
      O => a_4_CYMUXG2
    );
  a_4_CYSELG_38 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_4_G,
      O => a_4_CYSELG
    );
  a_4_SRINV_39 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0025,
      O => a_4_SRINV
    );
  a_4_CLKINV_40 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => inclk_BUFGP,
      O => a_4_CLKINV
    );
  a_6_LOGIC_ZERO_41 : X_ZERO
    port map (
      O => a_6_LOGIC_ZERO
    );
  a_6_DXMUX_42 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_6_XORF,
      O => a_6_DXMUX
    );
  a_6_XORF_43 : X_XOR2
    port map (
      I0 => a_6_CYINIT,
      I1 => a_6_F,
      O => a_6_XORF
    );
  a_6_CYMUXF : X_MUX2
    port map (
      IA => a_6_LOGIC_ZERO,
      IB => a_6_CYINIT,
      SEL => a_6_CYSELF,
      O => a_LPM_COUNTER_1_n0000_6_cyo
    );
  a_6_CYMUXF2_44 : X_MUX2
    port map (
      IA => a_6_LOGIC_ZERO,
      IB => a_6_LOGIC_ZERO,
      SEL => a_6_CYSELF,
      O => a_6_CYMUXF2
    );
  a_6_CYINIT_45 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_LPM_COUNTER_1_n0000_5_cyo,
      O => a_6_CYINIT
    );
  a_6_CYSELF_46 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_6_F,
      O => a_6_CYSELF
    );
  a_6_DYMUX_47 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_6_XORG,
      O => a_6_DYMUX
    );
  a_6_XORG_48 : X_XOR2
    port map (
      I0 => a_LPM_COUNTER_1_n0000_6_cyo,
      I1 => a_6_G,
      O => a_6_XORG
    );
  a_6_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_6_CYMUXFAST,
      O => a_LPM_COUNTER_1_n0000_7_cyo
    );
  a_6_FASTCARRY_49 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_LPM_COUNTER_1_n0000_5_cyo,
      O => a_6_FASTCARRY
    );
  a_6_CYAND_50 : X_AND2
    port map (
      I0 => a_6_CYSELG,
      I1 => a_6_CYSELF,
      O => a_6_CYAND
    );
  a_6_CYMUXFAST_51 : X_MUX2
    port map (
      IA =