szz_map.vhd

来自「VHDL设计的数字时钟」· VHDL 代码 · 共 2,022 行 · 第 1/5 页

  signal b_30_CYSELF : STD_LOGIC; 
  signal b_30_F : STD_LOGIC; 
  signal b_30_DYMUX : STD_LOGIC; 
  signal b_30_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_30_cyo : STD_LOGIC; 
  signal b_31_rt : STD_LOGIC; 
  signal b_30_SRINV : STD_LOGIC; 
  signal b_30_CLKINV : STD_LOGIC; 
  signal c_0_DXMUX : STD_LOGIC; 
  signal c_0_LOGIC_ONE : STD_LOGIC; 
  signal c_0_CYINIT : STD_LOGIC; 
  signal c_0_CYSELF : STD_LOGIC; 
  signal c_N3725 : STD_LOGIC; 
  signal c_0_BXINVNOT : STD_LOGIC; 
  signal c_0_DYMUX : STD_LOGIC; 
  signal c_0_XORG : STD_LOGIC; 
  signal c_0_CYMUXG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_0_cyo : STD_LOGIC; 
  signal c_0_LOGIC_ZERO : STD_LOGIC; 
  signal c_0_CYSELG : STD_LOGIC; 
  signal c_0_G : STD_LOGIC; 
  signal c_0_SRINV : STD_LOGIC; 
  signal c_0_CLKINV : STD_LOGIC; 
  signal c_2_DXMUX : STD_LOGIC; 
  signal c_2_XORF : STD_LOGIC; 
  signal c_2_CYINIT : STD_LOGIC; 
  signal c_2_F : STD_LOGIC; 
  signal c_2_DYMUX : STD_LOGIC; 
  signal c_2_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_2_cyo : STD_LOGIC; 
  signal c_2_CYSELF : STD_LOGIC; 
  signal c_2_CYMUXFAST : STD_LOGIC; 
  signal c_2_CYAND : STD_LOGIC; 
  signal c_2_FASTCARRY : STD_LOGIC; 
  signal c_2_CYMUXG2 : STD_LOGIC; 
  signal c_2_CYMUXF2 : STD_LOGIC; 
  signal c_2_LOGIC_ZERO : STD_LOGIC; 
  signal c_2_CYSELG : STD_LOGIC; 
  signal c_2_G : STD_LOGIC; 
  signal c_2_SRINV : STD_LOGIC; 
  signal c_2_CLKINV : STD_LOGIC; 
  signal c_4_DXMUX : STD_LOGIC; 
  signal c_4_XORF : STD_LOGIC; 
  signal c_4_CYINIT : STD_LOGIC; 
  signal c_4_F : STD_LOGIC; 
  signal c_4_DYMUX : STD_LOGIC; 
  signal c_4_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_4_cyo : STD_LOGIC; 
  signal c_4_CYSELF : STD_LOGIC; 
  signal c_4_CYMUXFAST : STD_LOGIC; 
  signal c_4_CYAND : STD_LOGIC; 
  signal c_4_FASTCARRY : STD_LOGIC; 
  signal c_4_CYMUXG2 : STD_LOGIC; 
  signal c_4_CYMUXF2 : STD_LOGIC; 
  signal c_4_LOGIC_ZERO : STD_LOGIC; 
  signal c_4_CYSELG : STD_LOGIC; 
  signal c_4_G : STD_LOGIC; 
  signal c_4_SRINV : STD_LOGIC; 
  signal c_4_CLKINV : STD_LOGIC; 
  signal c_6_DXMUX : STD_LOGIC; 
  signal c_6_XORF : STD_LOGIC; 
  signal c_6_CYINIT : STD_LOGIC; 
  signal c_6_F : STD_LOGIC; 
  signal c_6_DYMUX : STD_LOGIC; 
  signal c_6_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_6_cyo : STD_LOGIC; 
  signal c_6_CYSELF : STD_LOGIC; 
  signal c_6_CYMUXFAST : STD_LOGIC; 
  signal c_6_CYAND : STD_LOGIC; 
  signal c_6_FASTCARRY : STD_LOGIC; 
  signal c_6_CYMUXG2 : STD_LOGIC; 
  signal c_6_CYMUXF2 : STD_LOGIC; 
  signal c_6_LOGIC_ZERO : STD_LOGIC; 
  signal c_6_CYSELG : STD_LOGIC; 
  signal c_6_G : STD_LOGIC; 
  signal c_6_SRINV : STD_LOGIC; 
  signal c_6_CLKINV : STD_LOGIC; 
  signal c_8_DXMUX : STD_LOGIC; 
  signal c_8_XORF : STD_LOGIC; 
  signal c_8_CYINIT : STD_LOGIC; 
  signal c_8_F : STD_LOGIC; 
  signal c_8_DYMUX : STD_LOGIC; 
  signal c_8_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_8_cyo : STD_LOGIC; 
  signal c_8_CYSELF : STD_LOGIC; 
  signal c_8_CYMUXFAST : STD_LOGIC; 
  signal c_8_CYAND : STD_LOGIC; 
  signal c_8_FASTCARRY : STD_LOGIC; 
  signal c_8_CYMUXG2 : STD_LOGIC; 
  signal c_8_CYMUXF2 : STD_LOGIC; 
  signal c_8_LOGIC_ZERO : STD_LOGIC; 
  signal c_8_CYSELG : STD_LOGIC; 
  signal c_8_G : STD_LOGIC; 
  signal c_8_SRINV : STD_LOGIC; 
  signal c_8_CLKINV : STD_LOGIC; 
  signal c_10_DXMUX : STD_LOGIC; 
  signal c_10_XORF : STD_LOGIC; 
  signal c_10_CYINIT : STD_LOGIC; 
  signal c_10_F : STD_LOGIC; 
  signal c_10_DYMUX : STD_LOGIC; 
  signal c_10_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_10_cyo : STD_LOGIC; 
  signal c_10_CYSELF : STD_LOGIC; 
  signal c_10_CYMUXFAST : STD_LOGIC; 
  signal c_10_CYAND : STD_LOGIC; 
  signal c_10_FASTCARRY : STD_LOGIC; 
  signal c_10_CYMUXG2 : STD_LOGIC; 
  signal c_10_CYMUXF2 : STD_LOGIC; 
  signal c_10_LOGIC_ZERO : STD_LOGIC; 
  signal c_10_CYSELG : STD_LOGIC; 
  signal c_10_G : STD_LOGIC; 
  signal c_10_SRINV : STD_LOGIC; 
  signal c_10_CLKINV : STD_LOGIC; 
  signal c_12_DXMUX : STD_LOGIC; 
  signal c_12_XORF : STD_LOGIC; 
  signal c_12_CYINIT : STD_LOGIC; 
  signal c_12_F : STD_LOGIC; 
  signal c_12_DYMUX : STD_LOGIC; 
  signal c_12_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_12_cyo : STD_LOGIC; 
  signal c_12_CYSELF : STD_LOGIC; 
  signal c_12_CYMUXFAST : STD_LOGIC; 
  signal c_12_CYAND : STD_LOGIC; 
  signal c_12_FASTCARRY : STD_LOGIC; 
  signal c_12_CYMUXG2 : STD_LOGIC; 
  signal c_12_CYMUXF2 : STD_LOGIC; 
  signal c_12_LOGIC_ZERO : STD_LOGIC; 
  signal c_12_CYSELG : STD_LOGIC; 
  signal c_12_G : STD_LOGIC; 
  signal c_12_SRINV : STD_LOGIC; 
  signal c_12_CLKINV : STD_LOGIC; 
  signal c_14_DXMUX : STD_LOGIC; 
  signal c_14_XORF : STD_LOGIC; 
  signal c_14_CYINIT : STD_LOGIC; 
  signal c_14_F : STD_LOGIC; 
  signal c_14_DYMUX : STD_LOGIC; 
  signal c_14_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_14_cyo : STD_LOGIC; 
  signal c_14_CYSELF : STD_LOGIC; 
  signal c_14_CYMUXFAST : STD_LOGIC; 
  signal c_14_CYAND : STD_LOGIC; 
  signal c_14_FASTCARRY : STD_LOGIC; 
  signal c_14_CYMUXG2 : STD_LOGIC; 
  signal c_14_CYMUXF2 : STD_LOGIC; 
  signal c_14_LOGIC_ZERO : STD_LOGIC; 
  signal c_14_CYSELG : STD_LOGIC; 
  signal c_14_G : STD_LOGIC; 
  signal c_14_SRINV : STD_LOGIC; 
  signal c_14_CLKINV : STD_LOGIC; 
  signal c_16_DXMUX : STD_LOGIC; 
  signal c_16_XORF : STD_LOGIC; 
  signal c_16_CYINIT : STD_LOGIC; 
  signal c_16_F : STD_LOGIC; 
  signal c_16_DYMUX : STD_LOGIC; 
  signal c_16_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_16_cyo : STD_LOGIC; 
  signal c_16_CYSELF : STD_LOGIC; 
  signal c_16_CYMUXFAST : STD_LOGIC; 
  signal c_16_CYAND : STD_LOGIC; 
  signal c_16_FASTCARRY : STD_LOGIC; 
  signal c_16_CYMUXG2 : STD_LOGIC; 
  signal c_16_CYMUXF2 : STD_LOGIC; 
  signal c_16_LOGIC_ZERO : STD_LOGIC; 
  signal c_16_CYSELG : STD_LOGIC; 
  signal c_16_G : STD_LOGIC; 
  signal c_16_SRINV : STD_LOGIC; 
  signal c_16_CLKINV : STD_LOGIC; 
  signal c_18_DXMUX : STD_LOGIC; 
  signal c_18_XORF : STD_LOGIC; 
  signal c_18_CYINIT : STD_LOGIC; 
  signal c_18_F : STD_LOGIC; 
  signal c_18_DYMUX : STD_LOGIC; 
  signal c_18_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_18_cyo : STD_LOGIC; 
  signal c_18_CYSELF : STD_LOGIC; 
  signal c_18_CYMUXFAST : STD_LOGIC; 
  signal c_18_CYAND : STD_LOGIC; 
  signal c_18_FASTCARRY : STD_LOGIC; 
  signal c_18_CYMUXG2 : STD_LOGIC; 
  signal c_18_CYMUXF2 : STD_LOGIC; 
  signal c_18_LOGIC_ZERO : STD_LOGIC; 
  signal c_18_CYSELG : STD_LOGIC; 
  signal c_18_G : STD_LOGIC; 
  signal c_18_SRINV : STD_LOGIC; 
  signal c_18_CLKINV : STD_LOGIC; 
  signal c_20_DXMUX : STD_LOGIC; 
  signal c_20_XORF : STD_LOGIC; 
  signal c_20_CYINIT : STD_LOGIC; 
  signal c_20_F : STD_LOGIC; 
  signal c_20_DYMUX : STD_LOGIC; 
  signal c_20_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_20_cyo : STD_LOGIC; 
  signal c_20_CYSELF : STD_LOGIC; 
  signal c_20_CYMUXFAST : STD_LOGIC; 
  signal c_20_CYAND : STD_LOGIC; 
  signal c_20_FASTCARRY : STD_LOGIC; 
  signal c_20_CYMUXG2 : STD_LOGIC; 
  signal c_20_CYMUXF2 : STD_LOGIC; 
  signal c_20_LOGIC_ZERO : STD_LOGIC; 
  signal c_20_CYSELG : STD_LOGIC; 
  signal c_20_G : STD_LOGIC; 
  signal c_20_SRINV : STD_LOGIC; 
  signal c_20_CLKINV : STD_LOGIC; 
  signal c_22_DXMUX : STD_LOGIC; 
  signal c_22_XORF : STD_LOGIC; 
  signal c_22_CYINIT : STD_LOGIC; 
  signal c_22_F : STD_LOGIC; 
  signal c_22_DYMUX : STD_LOGIC; 
  signal c_22_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_22_cyo : STD_LOGIC; 
  signal c_22_CYSELF : STD_LOGIC; 
  signal c_22_CYMUXFAST : STD_LOGIC; 
  signal c_22_CYAND : STD_LOGIC; 
  signal c_22_FASTCARRY : STD_LOGIC; 
  signal c_22_CYMUXG2 : STD_LOGIC; 
  signal c_22_CYMUXF2 : STD_LOGIC; 
  signal c_22_LOGIC_ZERO : STD_LOGIC; 
  signal c_22_CYSELG : STD_LOGIC; 
  signal c_22_G : STD_LOGIC; 
  signal c_22_SRINV : STD_LOGIC; 
  signal c_22_CLKINV : STD_LOGIC; 
  signal c_24_DXMUX : STD_LOGIC; 
  signal c_24_XORF : STD_LOGIC; 
  signal c_24_CYINIT : STD_LOGIC; 
  signal c_24_F : STD_LOGIC; 
  signal c_24_DYMUX : STD_LOGIC; 
  signal c_24_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_24_cyo : STD_LOGIC; 
  signal c_24_CYSELF : STD_LOGIC; 
  signal c_24_CYMUXFAST : STD_LOGIC; 
  signal c_24_CYAND : STD_LOGIC; 
  signal c_24_FASTCARRY : STD_LOGIC; 
  signal c_24_CYMUXG2 : STD_LOGIC; 
  signal c_24_CYMUXF2 : STD_LOGIC; 
  signal c_24_LOGIC_ZERO : STD_LOGIC; 
  signal c_24_CYSELG : STD_LOGIC; 
  signal c_24_G : STD_LOGIC; 
  signal c_24_SRINV : STD_LOGIC; 
  signal c_24_CLKINV : STD_LOGIC; 
  signal c_26_DXMUX : STD_LOGIC; 
  signal c_26_XORF : STD_LOGIC; 
  signal c_26_CYINIT : STD_LOGIC; 
  signal c_26_F : STD_LOGIC; 
  signal c_26_DYMUX : STD_LOGIC; 
  signal c_26_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_26_cyo : STD_LOGIC; 
  signal c_26_CYSELF : STD_LOGIC; 
  signal c_26_CYMUXFAST : STD_LOGIC; 
  signal c_26_CYAND : STD_LOGIC; 
  signal c_26_FASTCARRY : STD_LOGIC; 
  signal c_26_CYMUXG2 : STD_LOGIC; 
  signal c_26_CYMUXF2 : STD_LOGIC; 
  signal c_26_LOGIC_ZERO : STD_LOGIC; 
  signal c_26_CYSELG : STD_LOGIC; 
  signal c_26_G : STD_LOGIC; 
  signal c_26_SRINV : STD_LOGIC; 
  signal c_26_CLKINV : STD_LOGIC; 
  signal c_28_DXMUX : STD_LOGIC; 
  signal c_28_XORF : STD_LOGIC; 
  signal c_28_CYINIT : STD_LOGIC; 
  signal c_28_F : STD_LOGIC; 
  signal c_28_DYMUX : STD_LOGIC; 
  signal c_28_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_28_cyo : STD_LOGIC; 
  signal c_28_CYSELF : STD_LOGIC; 
  signal c_28_CYMUXFAST : STD_LOGIC; 
  signal c_28_CYAND : STD_LOGIC; 
  signal c_28_FASTCARRY : STD_LOGIC; 
  signal c_28_CYMUXG2 : STD_LOGIC; 
  signal c_28_CYMUXF2 : STD_LOGIC; 
  signal c_28_LOGIC_ZERO : STD_LOGIC; 
  signal c_28_CYSELG : STD_LOGIC; 
  signal c_28_G : STD_LOGIC; 
  signal c_28_SRINV : STD_LOGIC; 
  signal c_28_CLKINV : STD_LOGIC; 
  signal c_30_DXMUX : STD_LOGIC; 
  signal c_30_XORF : STD_LOGIC; 
  signal c_30_LOGIC_ZERO : STD_LOGIC; 
  signal c_30_CYINIT : STD_LOGIC; 
  signal c_30_CYSELF : STD_LOGIC; 
  signal c_30_F : STD_LOGIC; 
  signal c_30_DYMUX : STD_LOGIC; 
  signal c_30_XORG : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_30_cyo : STD_LOGIC; 
  signal c_31_rt : STD_LOGIC; 
  signal c_30_SRINV : STD_LOGIC; 
  signal c_30_CLKINV : STD_LOGIC; 
  signal dout_0_ENABLE : STD_LOGIC; 
  signal dout_0_GTS_OR_T : STD_LOGIC; 
  signal dout_0_O : STD_LOGIC; 
  signal dout_1_OUTPUT_OTCLK1INVNOT : STD_LOGIC; 
  signal dout_1_ENABLE : STD_LOGIC; 
  signal dout_1_GTS_OR_T : STD_LOGIC; 
  signal dout_1_O : STD_LOGIC; 
  signal dout_2_OUTPUT_OTCLK1INVNOT : STD_LOGIC; 
  signal dout_2_ENABLE : STD_LOGIC; 
  signal dout_2_GTS_OR_T : STD_LOGIC; 
  signal dout_2_O : STD_LOGIC; 
  signal dout_3_ENABLE : STD_LOGIC; 
  signal dout_3_GTS_OR_T : STD_LOGIC; 
  signal dout_3_O : STD_LOGIC; 
  signal dout_4_ENABLE : STD_LOGIC; 
  signal dout_4_GTS_OR_T : STD_LOGIC; 
  signal dout_4_O : STD_LOGIC; 
  signal dout_5_ENABLE : STD_LOGIC; 
  signal dout_5_GTS_OR_T : STD_LOGIC; 
  signal dout_5_O : STD_LOGIC; 
  signal dout_6_OUTPUT_OTCLK1INVNOT : STD_LOGIC; 
  signal dout_6_ENABLE : STD_LOGIC; 
  signal dout_6_GTS_OR_T : STD_LOGIC; 
  signal dout_6_O : STD_LOGIC; 
  signal dout_7_ENABLE : STD_LOGIC; 
  signal dout_7_GTS_OR_T : STD_LOGIC; 
  signal dout_7_O : STD_LOGIC; 
  signal CE_ENABLE : STD_LOGIC; 
  signal CE_GTS_OR_T : STD_LOGIC; 
  signal CE_O : STD_LOGIC; 
  signal inclk_INBUF : STD_LOGIC; 
  signal speak_ENABLE : STD_LOGIC; 
  signal speak_GTS_OR_T : STD_LOGIC; 
  signal speak_O : STD_LOGIC; 
  signal selout_0_OUTPUT_OTCLK1INVNOT : STD_LOGIC; 
  signal selout_0_ENABLE : STD_LOGIC; 
  signal selout_0_GTS_OR_T : STD_LOGIC; 
  signal selout_0_O : STD_LOGIC; 
  signal selout_1_ENABLE : STD_LOGIC; 
  signal selout_1_GTS_OR_T : STD_LOGIC; 
  signal selout_1_O : STD_LOGIC; 
  signal selout_2_ENABLE : STD_LOGIC; 
  signal selout_2_GTS_OR_T : STD_LOGIC; 
  signal selout_2_O : STD_LOGIC; 
  signal selout_3_ENABLE : STD_LOGIC; 
  signal selout_3_GTS_OR_T : STD_LOGIC; 
  signal selout_3_O : STD_LOGIC; 
  signal md1_INBUF : STD_LOGIC; 
  signal md3_INBUF : STD_LOGIC; 
  signal md2_0_INBUF : STD_LOGIC; 
  signal md2_1_INBUF : STD_LOGIC; 
  signal inclk_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal CHOICE114_F5MUX : STD_LOGIC; 
  signal N10445 : STD_LOGIC; 
  signal CHOICE114_BXINV : STD_LOGIC; 
  signal N10443 : STD_LOGIC; 
  signal CHOICE157_F5MUX : STD_LOGIC; 
  signal N10440 : STD_LOGIC; 
  signal CHOICE157_BXINV : STD_LOGIC; 
  signal N10438 : STD_LOGIC; 
  signal N10338_F5MUX : STD_LOGIC; 
  signal N10450 : STD_LOGIC; 
  signal N10338_BXINV : STD_LOGIC; 
  signal N10448 : STD_LOGIC; 
  signal Q_n0042_F : STD_LOGIC; 
  signal Q_n0042_G : STD_LOGIC; 
  signal Q_n0037_F : STD_LOGIC; 
  signal Q_n0037_G : STD_LOGIC; 
  signal Q_n0038_F : STD_LOGIC; 
  signal Q_n0038_G : STD_LOGIC; 
  signal CHOICE683_F : STD_LOGIC; 
  signal CHOICE683_G : STD_LOGIC; 
  signal CHOICE645_F : STD_LOGIC; 
  signal CHOICE645_G : STD_LOGIC; 
  signal CHOICE533_F : STD_LOGIC; 
  signal CHOICE533_G : STD_LOGIC; 
  signal Q_n0036_F : STD_LOGIC; 
  signal Q_n0036_G : STD_LOGIC; 
  signal CHOICE586_F : STD_LOGIC; 
  signal CHOICE586_G : STD_LOGIC; 
  signal Q_n0034_F : STD_LOGIC; 
  signal Q_n0034_G : STD_LOGIC; 
  signal N5818_F : STD_LOGIC; 
  signal N5818_G : STD_LOGIC; 
  signal Q_n0025_F : STD_LOGIC; 
  signal Q_n0025_G : STD_LOGIC; 
  signal Q_n0027_F : STD_LOGIC; 
  signal Q_n0027_G : STD_LOGIC; 
  signal Q_n0028_F : STD_LOGIC; 
  signal Q_n0028_G : STD_LOGIC; 
  signal Q_n0040_F : STD_LOGIC; 
  signal Q_n0040_G : STD_LOGIC; 
  signal sel_2_F : STD_LOGIC; 
  signal sel_2_DYMUX : STD_LOGIC; 
  signal sel_2_SRINV : STD_LOGIC; 
  signal sel_2_CLKINV : STD_LOGIC; 
  signal hou1_3_DXMUX : STD_LOGIC; 
  signal hou1_3_DYMUX : STD_LOGIC; 
  signal hou1_3_SRINV : STD_LOGIC; 
  signal hou1_3_CLKINV : STD_LOGIC; 
  signal hou1_3_CEINV : STD_LOGIC; 
  signal hou2_3_DXMUX : STD_LOGIC; 
  signal hou2_3_DYMUX : STD_LOGIC; 
  signal hou2_3_SRINV : STD_LOGIC; 
  signal hou2_3_CLKINV : STD_LOGIC; 
  signal hou2_3_CEINV : STD_LOGIC; 
  signal min1_3_DXMUX : STD_LOGIC; 
  signal min1_3_DYMUX : STD_LOGIC; 
  signal min1_3_SRINV : STD_LOGIC; 
  signal min1_3_CLKINV : STD_LOGIC; 
  signal min1_3_CEINV : STD_LOGIC; 
  signal min2_3_DXMUX : STD_LOGIC; 
  signal min2_3_DYMUX : STD_LOGIC; 
  signal min2_3_SRINV : STD_LOGIC; 
  signal min2_3_CLKINV : STD_LOGIC; 
  signal min2_3_CEINV : STD_LOGIC; 
  signal sec1_3_DXMUX : STD_LOGIC; 
  signal sec1_3_DYMUX : STD_LOGIC;