szz_map.vhd

来自「VHDL设计的数字时钟」· VHDL 代码 · 共 2,022 行 · 第 1/5 页

  signal a_16_DYMUX : STD_LOGIC; 
  signal a_16_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_16_cyo : STD_LOGIC; 
  signal a_16_CYSELF : STD_LOGIC; 
  signal a_16_CYMUXFAST : STD_LOGIC; 
  signal a_16_CYAND : STD_LOGIC; 
  signal a_16_FASTCARRY : STD_LOGIC; 
  signal a_16_CYMUXG2 : STD_LOGIC; 
  signal a_16_CYMUXF2 : STD_LOGIC; 
  signal a_16_LOGIC_ZERO : STD_LOGIC; 
  signal a_16_CYSELG : STD_LOGIC; 
  signal a_16_G : STD_LOGIC; 
  signal a_16_SRINV : STD_LOGIC; 
  signal a_16_CLKINV : STD_LOGIC; 
  signal a_18_DXMUX : STD_LOGIC; 
  signal a_18_XORF : STD_LOGIC; 
  signal a_18_CYINIT : STD_LOGIC; 
  signal a_18_F : STD_LOGIC; 
  signal a_18_DYMUX : STD_LOGIC; 
  signal a_18_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_18_cyo : STD_LOGIC; 
  signal a_18_CYSELF : STD_LOGIC; 
  signal a_18_CYMUXFAST : STD_LOGIC; 
  signal a_18_CYAND : STD_LOGIC; 
  signal a_18_FASTCARRY : STD_LOGIC; 
  signal a_18_CYMUXG2 : STD_LOGIC; 
  signal a_18_CYMUXF2 : STD_LOGIC; 
  signal a_18_LOGIC_ZERO : STD_LOGIC; 
  signal a_18_CYSELG : STD_LOGIC; 
  signal a_18_G : STD_LOGIC; 
  signal a_18_SRINV : STD_LOGIC; 
  signal a_18_CLKINV : STD_LOGIC; 
  signal a_20_DXMUX : STD_LOGIC; 
  signal a_20_XORF : STD_LOGIC; 
  signal a_20_CYINIT : STD_LOGIC; 
  signal a_20_F : STD_LOGIC; 
  signal a_20_DYMUX : STD_LOGIC; 
  signal a_20_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_20_cyo : STD_LOGIC; 
  signal a_20_CYSELF : STD_LOGIC; 
  signal a_20_CYMUXFAST : STD_LOGIC; 
  signal a_20_CYAND : STD_LOGIC; 
  signal a_20_FASTCARRY : STD_LOGIC; 
  signal a_20_CYMUXG2 : STD_LOGIC; 
  signal a_20_CYMUXF2 : STD_LOGIC; 
  signal a_20_LOGIC_ZERO : STD_LOGIC; 
  signal a_20_CYSELG : STD_LOGIC; 
  signal a_20_G : STD_LOGIC; 
  signal a_20_SRINV : STD_LOGIC; 
  signal a_20_CLKINV : STD_LOGIC; 
  signal a_22_DXMUX : STD_LOGIC; 
  signal a_22_XORF : STD_LOGIC; 
  signal a_22_CYINIT : STD_LOGIC; 
  signal a_22_F : STD_LOGIC; 
  signal a_22_DYMUX : STD_LOGIC; 
  signal a_22_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_22_cyo : STD_LOGIC; 
  signal a_22_CYSELF : STD_LOGIC; 
  signal a_22_CYMUXFAST : STD_LOGIC; 
  signal a_22_CYAND : STD_LOGIC; 
  signal a_22_FASTCARRY : STD_LOGIC; 
  signal a_22_CYMUXG2 : STD_LOGIC; 
  signal a_22_CYMUXF2 : STD_LOGIC; 
  signal a_22_LOGIC_ZERO : STD_LOGIC; 
  signal a_22_CYSELG : STD_LOGIC; 
  signal a_22_G : STD_LOGIC; 
  signal a_22_SRINV : STD_LOGIC; 
  signal a_22_CLKINV : STD_LOGIC; 
  signal a_24_DXMUX : STD_LOGIC; 
  signal a_24_XORF : STD_LOGIC; 
  signal a_24_CYINIT : STD_LOGIC; 
  signal a_24_F : STD_LOGIC; 
  signal a_24_DYMUX : STD_LOGIC; 
  signal a_24_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_24_cyo : STD_LOGIC; 
  signal a_24_CYSELF : STD_LOGIC; 
  signal a_24_CYMUXFAST : STD_LOGIC; 
  signal a_24_CYAND : STD_LOGIC; 
  signal a_24_FASTCARRY : STD_LOGIC; 
  signal a_24_CYMUXG2 : STD_LOGIC; 
  signal a_24_CYMUXF2 : STD_LOGIC; 
  signal a_24_LOGIC_ZERO : STD_LOGIC; 
  signal a_24_CYSELG : STD_LOGIC; 
  signal a_24_G : STD_LOGIC; 
  signal a_24_SRINV : STD_LOGIC; 
  signal a_24_CLKINV : STD_LOGIC; 
  signal a_26_DXMUX : STD_LOGIC; 
  signal a_26_XORF : STD_LOGIC; 
  signal a_26_CYINIT : STD_LOGIC; 
  signal a_26_F : STD_LOGIC; 
  signal a_26_DYMUX : STD_LOGIC; 
  signal a_26_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_26_cyo : STD_LOGIC; 
  signal a_26_CYSELF : STD_LOGIC; 
  signal a_26_CYMUXFAST : STD_LOGIC; 
  signal a_26_CYAND : STD_LOGIC; 
  signal a_26_FASTCARRY : STD_LOGIC; 
  signal a_26_CYMUXG2 : STD_LOGIC; 
  signal a_26_CYMUXF2 : STD_LOGIC; 
  signal a_26_LOGIC_ZERO : STD_LOGIC; 
  signal a_26_CYSELG : STD_LOGIC; 
  signal a_26_G : STD_LOGIC; 
  signal a_26_SRINV : STD_LOGIC; 
  signal a_26_CLKINV : STD_LOGIC; 
  signal a_28_DXMUX : STD_LOGIC; 
  signal a_28_XORF : STD_LOGIC; 
  signal a_28_CYINIT : STD_LOGIC; 
  signal a_28_F : STD_LOGIC; 
  signal a_28_DYMUX : STD_LOGIC; 
  signal a_28_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_28_cyo : STD_LOGIC; 
  signal a_28_CYSELF : STD_LOGIC; 
  signal a_28_CYMUXFAST : STD_LOGIC; 
  signal a_28_CYAND : STD_LOGIC; 
  signal a_28_FASTCARRY : STD_LOGIC; 
  signal a_28_CYMUXG2 : STD_LOGIC; 
  signal a_28_CYMUXF2 : STD_LOGIC; 
  signal a_28_LOGIC_ZERO : STD_LOGIC; 
  signal a_28_CYSELG : STD_LOGIC; 
  signal a_28_G : STD_LOGIC; 
  signal a_28_SRINV : STD_LOGIC; 
  signal a_28_CLKINV : STD_LOGIC; 
  signal a_30_DXMUX : STD_LOGIC; 
  signal a_30_XORF : STD_LOGIC; 
  signal a_30_LOGIC_ZERO : STD_LOGIC; 
  signal a_30_CYINIT : STD_LOGIC; 
  signal a_30_CYSELF : STD_LOGIC; 
  signal a_30_F : STD_LOGIC; 
  signal a_30_DYMUX : STD_LOGIC; 
  signal a_30_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_30_cyo : STD_LOGIC; 
  signal a_31_rt : STD_LOGIC; 
  signal a_30_SRINV : STD_LOGIC; 
  signal a_30_CLKINV : STD_LOGIC; 
  signal b_0_DXMUX : STD_LOGIC; 
  signal b_0_LOGIC_ONE : STD_LOGIC; 
  signal b_0_CYINIT : STD_LOGIC; 
  signal b_0_CYSELF : STD_LOGIC; 
  signal b_N3725 : STD_LOGIC; 
  signal b_0_BXINVNOT : STD_LOGIC; 
  signal b_0_DYMUX : STD_LOGIC; 
  signal b_0_XORG : STD_LOGIC; 
  signal b_0_CYMUXG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_0_cyo : STD_LOGIC; 
  signal b_0_LOGIC_ZERO : STD_LOGIC; 
  signal b_0_CYSELG : STD_LOGIC; 
  signal b_0_G : STD_LOGIC; 
  signal b_0_SRINV : STD_LOGIC; 
  signal b_0_CLKINV : STD_LOGIC; 
  signal b_2_DXMUX : STD_LOGIC; 
  signal b_2_XORF : STD_LOGIC; 
  signal b_2_CYINIT : STD_LOGIC; 
  signal b_2_F : STD_LOGIC; 
  signal b_2_DYMUX : STD_LOGIC; 
  signal b_2_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_2_cyo : STD_LOGIC; 
  signal b_2_CYSELF : STD_LOGIC; 
  signal b_2_CYMUXFAST : STD_LOGIC; 
  signal b_2_CYAND : STD_LOGIC; 
  signal b_2_FASTCARRY : STD_LOGIC; 
  signal b_2_CYMUXG2 : STD_LOGIC; 
  signal b_2_CYMUXF2 : STD_LOGIC; 
  signal b_2_LOGIC_ZERO : STD_LOGIC; 
  signal b_2_CYSELG : STD_LOGIC; 
  signal b_2_G : STD_LOGIC; 
  signal b_2_SRINV : STD_LOGIC; 
  signal b_2_CLKINV : STD_LOGIC; 
  signal b_4_DXMUX : STD_LOGIC; 
  signal b_4_XORF : STD_LOGIC; 
  signal b_4_CYINIT : STD_LOGIC; 
  signal b_4_F : STD_LOGIC; 
  signal b_4_DYMUX : STD_LOGIC; 
  signal b_4_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_4_cyo : STD_LOGIC; 
  signal b_4_CYSELF : STD_LOGIC; 
  signal b_4_CYMUXFAST : STD_LOGIC; 
  signal b_4_CYAND : STD_LOGIC; 
  signal b_4_FASTCARRY : STD_LOGIC; 
  signal b_4_CYMUXG2 : STD_LOGIC; 
  signal b_4_CYMUXF2 : STD_LOGIC; 
  signal b_4_LOGIC_ZERO : STD_LOGIC; 
  signal b_4_CYSELG : STD_LOGIC; 
  signal b_4_G : STD_LOGIC; 
  signal b_4_SRINV : STD_LOGIC; 
  signal b_4_CLKINV : STD_LOGIC; 
  signal b_6_DXMUX : STD_LOGIC; 
  signal b_6_XORF : STD_LOGIC; 
  signal b_6_CYINIT : STD_LOGIC; 
  signal b_6_F : STD_LOGIC; 
  signal b_6_DYMUX : STD_LOGIC; 
  signal b_6_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_6_cyo : STD_LOGIC; 
  signal b_6_CYSELF : STD_LOGIC; 
  signal b_6_CYMUXFAST : STD_LOGIC; 
  signal b_6_CYAND : STD_LOGIC; 
  signal b_6_FASTCARRY : STD_LOGIC; 
  signal b_6_CYMUXG2 : STD_LOGIC; 
  signal b_6_CYMUXF2 : STD_LOGIC; 
  signal b_6_LOGIC_ZERO : STD_LOGIC; 
  signal b_6_CYSELG : STD_LOGIC; 
  signal b_6_G : STD_LOGIC; 
  signal b_6_SRINV : STD_LOGIC; 
  signal b_6_CLKINV : STD_LOGIC; 
  signal b_8_DXMUX : STD_LOGIC; 
  signal b_8_XORF : STD_LOGIC; 
  signal b_8_CYINIT : STD_LOGIC; 
  signal b_8_F : STD_LOGIC; 
  signal b_8_DYMUX : STD_LOGIC; 
  signal b_8_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_8_cyo : STD_LOGIC; 
  signal b_8_CYSELF : STD_LOGIC; 
  signal b_8_CYMUXFAST : STD_LOGIC; 
  signal b_8_CYAND : STD_LOGIC; 
  signal b_8_FASTCARRY : STD_LOGIC; 
  signal b_8_CYMUXG2 : STD_LOGIC; 
  signal b_8_CYMUXF2 : STD_LOGIC; 
  signal b_8_LOGIC_ZERO : STD_LOGIC; 
  signal b_8_CYSELG : STD_LOGIC; 
  signal b_8_G : STD_LOGIC; 
  signal b_8_SRINV : STD_LOGIC; 
  signal b_8_CLKINV : STD_LOGIC; 
  signal b_10_DXMUX : STD_LOGIC; 
  signal b_10_XORF : STD_LOGIC; 
  signal b_10_CYINIT : STD_LOGIC; 
  signal b_10_F : STD_LOGIC; 
  signal b_10_DYMUX : STD_LOGIC; 
  signal b_10_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_10_cyo : STD_LOGIC; 
  signal b_10_CYSELF : STD_LOGIC; 
  signal b_10_CYMUXFAST : STD_LOGIC; 
  signal b_10_CYAND : STD_LOGIC; 
  signal b_10_FASTCARRY : STD_LOGIC; 
  signal b_10_CYMUXG2 : STD_LOGIC; 
  signal b_10_CYMUXF2 : STD_LOGIC; 
  signal b_10_LOGIC_ZERO : STD_LOGIC; 
  signal b_10_CYSELG : STD_LOGIC; 
  signal b_10_G : STD_LOGIC; 
  signal b_10_SRINV : STD_LOGIC; 
  signal b_10_CLKINV : STD_LOGIC; 
  signal b_12_DXMUX : STD_LOGIC; 
  signal b_12_XORF : STD_LOGIC; 
  signal b_12_CYINIT : STD_LOGIC; 
  signal b_12_F : STD_LOGIC; 
  signal b_12_DYMUX : STD_LOGIC; 
  signal b_12_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_12_cyo : STD_LOGIC; 
  signal b_12_CYSELF : STD_LOGIC; 
  signal b_12_CYMUXFAST : STD_LOGIC; 
  signal b_12_CYAND : STD_LOGIC; 
  signal b_12_FASTCARRY : STD_LOGIC; 
  signal b_12_CYMUXG2 : STD_LOGIC; 
  signal b_12_CYMUXF2 : STD_LOGIC; 
  signal b_12_LOGIC_ZERO : STD_LOGIC; 
  signal b_12_CYSELG : STD_LOGIC; 
  signal b_12_G : STD_LOGIC; 
  signal b_12_SRINV : STD_LOGIC; 
  signal b_12_CLKINV : STD_LOGIC; 
  signal b_14_DXMUX : STD_LOGIC; 
  signal b_14_XORF : STD_LOGIC; 
  signal b_14_CYINIT : STD_LOGIC; 
  signal b_14_F : STD_LOGIC; 
  signal b_14_DYMUX : STD_LOGIC; 
  signal b_14_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_14_cyo : STD_LOGIC; 
  signal b_14_CYSELF : STD_LOGIC; 
  signal b_14_CYMUXFAST : STD_LOGIC; 
  signal b_14_CYAND : STD_LOGIC; 
  signal b_14_FASTCARRY : STD_LOGIC; 
  signal b_14_CYMUXG2 : STD_LOGIC; 
  signal b_14_CYMUXF2 : STD_LOGIC; 
  signal b_14_LOGIC_ZERO : STD_LOGIC; 
  signal b_14_CYSELG : STD_LOGIC; 
  signal b_14_G : STD_LOGIC; 
  signal b_14_SRINV : STD_LOGIC; 
  signal b_14_CLKINV : STD_LOGIC; 
  signal b_16_DXMUX : STD_LOGIC; 
  signal b_16_XORF : STD_LOGIC; 
  signal b_16_CYINIT : STD_LOGIC; 
  signal b_16_F : STD_LOGIC; 
  signal b_16_DYMUX : STD_LOGIC; 
  signal b_16_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_16_cyo : STD_LOGIC; 
  signal b_16_CYSELF : STD_LOGIC; 
  signal b_16_CYMUXFAST : STD_LOGIC; 
  signal b_16_CYAND : STD_LOGIC; 
  signal b_16_FASTCARRY : STD_LOGIC; 
  signal b_16_CYMUXG2 : STD_LOGIC; 
  signal b_16_CYMUXF2 : STD_LOGIC; 
  signal b_16_LOGIC_ZERO : STD_LOGIC; 
  signal b_16_CYSELG : STD_LOGIC; 
  signal b_16_G : STD_LOGIC; 
  signal b_16_SRINV : STD_LOGIC; 
  signal b_16_CLKINV : STD_LOGIC; 
  signal b_18_DXMUX : STD_LOGIC; 
  signal b_18_XORF : STD_LOGIC; 
  signal b_18_CYINIT : STD_LOGIC; 
  signal b_18_F : STD_LOGIC; 
  signal b_18_DYMUX : STD_LOGIC; 
  signal b_18_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_18_cyo : STD_LOGIC; 
  signal b_18_CYSELF : STD_LOGIC; 
  signal b_18_CYMUXFAST : STD_LOGIC; 
  signal b_18_CYAND : STD_LOGIC; 
  signal b_18_FASTCARRY : STD_LOGIC; 
  signal b_18_CYMUXG2 : STD_LOGIC; 
  signal b_18_CYMUXF2 : STD_LOGIC; 
  signal b_18_LOGIC_ZERO : STD_LOGIC; 
  signal b_18_CYSELG : STD_LOGIC; 
  signal b_18_G : STD_LOGIC; 
  signal b_18_SRINV : STD_LOGIC; 
  signal b_18_CLKINV : STD_LOGIC; 
  signal b_20_DXMUX : STD_LOGIC; 
  signal b_20_XORF : STD_LOGIC; 
  signal b_20_CYINIT : STD_LOGIC; 
  signal b_20_F : STD_LOGIC; 
  signal b_20_DYMUX : STD_LOGIC; 
  signal b_20_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_20_cyo : STD_LOGIC; 
  signal b_20_CYSELF : STD_LOGIC; 
  signal b_20_CYMUXFAST : STD_LOGIC; 
  signal b_20_CYAND : STD_LOGIC; 
  signal b_20_FASTCARRY : STD_LOGIC; 
  signal b_20_CYMUXG2 : STD_LOGIC; 
  signal b_20_CYMUXF2 : STD_LOGIC; 
  signal b_20_LOGIC_ZERO : STD_LOGIC; 
  signal b_20_CYSELG : STD_LOGIC; 
  signal b_20_G : STD_LOGIC; 
  signal b_20_SRINV : STD_LOGIC; 
  signal b_20_CLKINV : STD_LOGIC; 
  signal b_22_DXMUX : STD_LOGIC; 
  signal b_22_XORF : STD_LOGIC; 
  signal b_22_CYINIT : STD_LOGIC; 
  signal b_22_F : STD_LOGIC; 
  signal b_22_DYMUX : STD_LOGIC; 
  signal b_22_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_22_cyo : STD_LOGIC; 
  signal b_22_CYSELF : STD_LOGIC; 
  signal b_22_CYMUXFAST : STD_LOGIC; 
  signal b_22_CYAND : STD_LOGIC; 
  signal b_22_FASTCARRY : STD_LOGIC; 
  signal b_22_CYMUXG2 : STD_LOGIC; 
  signal b_22_CYMUXF2 : STD_LOGIC; 
  signal b_22_LOGIC_ZERO : STD_LOGIC; 
  signal b_22_CYSELG : STD_LOGIC; 
  signal b_22_G : STD_LOGIC; 
  signal b_22_SRINV : STD_LOGIC; 
  signal b_22_CLKINV : STD_LOGIC; 
  signal b_24_DXMUX : STD_LOGIC; 
  signal b_24_XORF : STD_LOGIC; 
  signal b_24_CYINIT : STD_LOGIC; 
  signal b_24_F : STD_LOGIC; 
  signal b_24_DYMUX : STD_LOGIC; 
  signal b_24_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_24_cyo : STD_LOGIC; 
  signal b_24_CYSELF : STD_LOGIC; 
  signal b_24_CYMUXFAST : STD_LOGIC; 
  signal b_24_CYAND : STD_LOGIC; 
  signal b_24_FASTCARRY : STD_LOGIC; 
  signal b_24_CYMUXG2 : STD_LOGIC; 
  signal b_24_CYMUXF2 : STD_LOGIC; 
  signal b_24_LOGIC_ZERO : STD_LOGIC; 
  signal b_24_CYSELG : STD_LOGIC; 
  signal b_24_G : STD_LOGIC; 
  signal b_24_SRINV : STD_LOGIC; 
  signal b_24_CLKINV : STD_LOGIC; 
  signal b_26_DXMUX : STD_LOGIC; 
  signal b_26_XORF : STD_LOGIC; 
  signal b_26_CYINIT : STD_LOGIC; 
  signal b_26_F : STD_LOGIC; 
  signal b_26_DYMUX : STD_LOGIC; 
  signal b_26_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_26_cyo : STD_LOGIC; 
  signal b_26_CYSELF : STD_LOGIC; 
  signal b_26_CYMUXFAST : STD_LOGIC; 
  signal b_26_CYAND : STD_LOGIC; 
  signal b_26_FASTCARRY : STD_LOGIC; 
  signal b_26_CYMUXG2 : STD_LOGIC; 
  signal b_26_CYMUXF2 : STD_LOGIC; 
  signal b_26_LOGIC_ZERO : STD_LOGIC; 
  signal b_26_CYSELG : STD_LOGIC; 
  signal b_26_G : STD_LOGIC; 
  signal b_26_SRINV : STD_LOGIC; 
  signal b_26_CLKINV : STD_LOGIC; 
  signal b_28_DXMUX : STD_LOGIC; 
  signal b_28_XORF : STD_LOGIC; 
  signal b_28_CYINIT : STD_LOGIC; 
  signal b_28_F : STD_LOGIC; 
  signal b_28_DYMUX : STD_LOGIC; 
  signal b_28_XORG : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_28_cyo : STD_LOGIC; 
  signal b_28_CYSELF : STD_LOGIC; 
  signal b_28_CYMUXFAST : STD_LOGIC; 
  signal b_28_CYAND : STD_LOGIC; 
  signal b_28_FASTCARRY : STD_LOGIC; 
  signal b_28_CYMUXG2 : STD_LOGIC; 
  signal b_28_CYMUXF2 : STD_LOGIC; 
  signal b_28_LOGIC_ZERO : STD_LOGIC; 
  signal b_28_CYSELG : STD_LOGIC; 
  signal b_28_G : STD_LOGIC; 
  signal b_28_SRINV : STD_LOGIC; 
  signal b_28_CLKINV : STD_LOGIC; 
  signal b_30_DXMUX : STD_LOGIC; 
  signal b_30_XORF : STD_LOGIC; 
  signal b_30_LOGIC_ZERO : STD_LOGIC; 
  signal b_30_CYINIT : STD_LOGIC;