szz_map.vhd

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-- Xilinx Vhdl netlist produced by netgen application (version G.38)
-- Command       : -intstyle ise -s 4 -pcf szz.pcf -ngm szz.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim szz_map.ncd szz_map.vhd 
-- Input file    : szz_map.ncd
-- Output file   : szz_map.vhd
-- Design name   : szz
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : 3s200pq208-4 (PRODUCTION 1.35 2004-11-11)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity szz is
  port (
    speak : out STD_LOGIC; 
    CE : out STD_LOGIC; 
    md1 : in STD_LOGIC := 'X'; 
    inclk : in STD_LOGIC := 'X'; 
    md3 : in STD_LOGIC := 'X'; 
    dout : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    selout : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    md2 : in STD_LOGIC_VECTOR ( 1 downto 0 ) 
  );
end szz;

architecture Structure of szz is
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal inclk_BUFGP : STD_LOGIC; 
  signal Q_n0025 : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_1_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_3_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_5_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_7_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_9_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_11_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_13_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_15_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_17_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_19_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_21_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_23_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_25_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_27_cyo : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_29_cyo : STD_LOGIC; 
  signal Q_n0028 : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_1_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_3_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_5_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_7_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_9_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_11_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_13_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_15_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_17_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_19_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_21_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_23_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_25_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_27_cyo : STD_LOGIC; 
  signal b_LPM_COUNTER_1_n0000_29_cyo : STD_LOGIC; 
  signal Q_n0027 : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_1_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_3_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_5_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_7_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_9_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_11_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_13_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_15_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_17_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_19_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_21_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_23_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_25_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_27_cyo : STD_LOGIC; 
  signal c_LPM_COUNTER_1_n0000_29_cyo : STD_LOGIC; 
  signal Q_n0055 : STD_LOGIC; 
  signal inclk_BUFGP_IBUFG : STD_LOGIC; 
  signal speak_N402 : STD_LOGIC; 
  signal clk1 : STD_LOGIC; 
  signal clk2 : STD_LOGIC; 
  signal N5887 : STD_LOGIC; 
  signal md1_IBUF : STD_LOGIC; 
  signal md3_IBUF : STD_LOGIC; 
  signal md2_0_IBUF : STD_LOGIC; 
  signal md2_1_IBUF : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal CHOICE114 : STD_LOGIC; 
  signal Q_n0056 : STD_LOGIC; 
  signal N5685 : STD_LOGIC; 
  signal CHOICE157 : STD_LOGIC; 
  signal N10338 : STD_LOGIC; 
  signal Q_n0127 : STD_LOGIC; 
  signal Q_n0043 : STD_LOGIC; 
  signal Q_n0042 : STD_LOGIC; 
  signal N5911 : STD_LOGIC; 
  signal Q_n0125 : STD_LOGIC; 
  signal Q_n0126 : STD_LOGIC; 
  signal Q_n0037 : STD_LOGIC; 
  signal N5818 : STD_LOGIC; 
  signal Q_n0038 : STD_LOGIC; 
  signal Q_n0129 : STD_LOGIC; 
  signal CHOICE683 : STD_LOGIC; 
  signal Q_n002542_O : STD_LOGIC; 
  signal CHOICE644 : STD_LOGIC; 
  signal CHOICE645 : STD_LOGIC; 
  signal Q_n002837_O : STD_LOGIC; 
  signal CHOICE532 : STD_LOGIC; 
  signal CHOICE533 : STD_LOGIC; 
  signal Q_n003629_O : STD_LOGIC; 
  signal Q_n0123 : STD_LOGIC; 
  signal Q_n0036 : STD_LOGIC; 
  signal Q_n002744_O : STD_LOGIC; 
  signal CHOICE585 : STD_LOGIC; 
  signal CHOICE586 : STD_LOGIC; 
  signal CHOICE495 : STD_LOGIC; 
  signal Q_n0034 : STD_LOGIC; 
  signal CHOICE623 : STD_LOGIC; 
  signal CHOICE630 : STD_LOGIC; 
  signal Q_n0025157_O : STD_LOGIC; 
  signal CHOICE653 : STD_LOGIC; 
  signal CHOICE660 : STD_LOGIC; 
  signal CHOICE668 : STD_LOGIC; 
  signal CHOICE675 : STD_LOGIC; 
  signal CHOICE567 : STD_LOGIC; 
  signal CHOICE572 : STD_LOGIC; 
  signal Q_n0027159_O : STD_LOGIC; 
  signal CHOICE594 : STD_LOGIC; 
  signal CHOICE601 : STD_LOGIC; 
  signal CHOICE609 : STD_LOGIC; 
  signal CHOICE616 : STD_LOGIC; 
  signal CHOICE513 : STD_LOGIC; 
  signal CHOICE517 : STD_LOGIC; 
  signal Q_n0028144_O : STD_LOGIC; 
  signal CHOICE538 : STD_LOGIC; 
  signal CHOICE544 : STD_LOGIC; 
  signal CHOICE552 : STD_LOGIC; 
  signal CHOICE559 : STD_LOGIC; 
  signal N9038 : STD_LOGIC; 
  signal Q_n0040 : STD_LOGIC; 
  signal N5858 : STD_LOGIC; 
  signal Q_n0035 : STD_LOGIC; 
  signal clk : STD_LOGIC; 
  signal Q_n0039 : STD_LOGIC; 
  signal Q_n0041 : STD_LOGIC; 
  signal Q_n0045 : STD_LOGIC; 
  signal Q_n0044 : STD_LOGIC; 
  signal Q_n0047 : STD_LOGIC; 
  signal Q_n0046 : STD_LOGIC; 
  signal Q_n0049 : STD_LOGIC; 
  signal Q_n0048 : STD_LOGIC; 
  signal Q_n0050 : STD_LOGIC; 
  signal N8992 : STD_LOGIC; 
  signal Q_n0140 : STD_LOGIC; 
  signal CHOICE502 : STD_LOGIC; 
  signal Q_n0141 : STD_LOGIC; 
  signal CHOICE128 : STD_LOGIC; 
  signal N10322 : STD_LOGIC; 
  signal Q_n0142 : STD_LOGIC; 
  signal CHOICE130 : STD_LOGIC; 
  signal Q_n0147 : STD_LOGIC; 
  signal N10407 : STD_LOGIC; 
  signal Q_n0144 : STD_LOGIC; 
  signal N8940 : STD_LOGIC; 
  signal Q_n0057 : STD_LOGIC; 
  signal CHOICE91 : STD_LOGIC; 
  signal Q_n0058 : STD_LOGIC; 
  signal CHOICE119 : STD_LOGIC; 
  signal N10354 : STD_LOGIC; 
  signal N10383 : STD_LOGIC; 
  signal CHOICE181 : STD_LOGIC; 
  signal CHOICE245 : STD_LOGIC; 
  signal CHOICE508 : STD_LOGIC; 
  signal N10374 : STD_LOGIC; 
  signal N10330 : STD_LOGIC; 
  signal N5863 : STD_LOGIC; 
  signal CHOICE44 : STD_LOGIC; 
  signal N6059 : STD_LOGIC; 
  signal N5812 : STD_LOGIC; 
  signal N5717 : STD_LOGIC; 
  signal N5806 : STD_LOGIC; 
  signal CHOICE74 : STD_LOGIC; 
  signal CHOICE212 : STD_LOGIC; 
  signal CHOICE350 : STD_LOGIC; 
  signal CHOICE256 : STD_LOGIC; 
  signal N5676 : STD_LOGIC; 
  signal N5610 : STD_LOGIC; 
  signal N10424 : STD_LOGIC; 
  signal N5917 : STD_LOGIC; 
  signal CHOICE399 : STD_LOGIC; 
  signal N10342 : STD_LOGIC; 
  signal N10326 : STD_LOGIC; 
  signal N10379 : STD_LOGIC; 
  signal CHOICE93 : STD_LOGIC; 
  signal CHOICE59 : STD_LOGIC; 
  signal CHOICE67 : STD_LOGIC; 
  signal CHOICE268 : STD_LOGIC; 
  signal CHOICE232 : STD_LOGIC; 
  signal N5848 : STD_LOGIC; 
  signal N5893 : STD_LOGIC; 
  signal N5870 : STD_LOGIC; 
  signal N5800 : STD_LOGIC; 
  signal CHOICE28 : STD_LOGIC; 
  signal N5899 : STD_LOGIC; 
  signal CHOICE403 : STD_LOGIC; 
  signal CHOICE22 : STD_LOGIC; 
  signal CHOICE29 : STD_LOGIC; 
  signal CHOICE50 : STD_LOGIC; 
  signal CHOICE51 : STD_LOGIC; 
  signal CHOICE36 : STD_LOGIC; 
  signal CHOICE52 : STD_LOGIC; 
  signal CHOICE65 : STD_LOGIC; 
  signal N10298 : STD_LOGIC; 
  signal CHOICE279 : STD_LOGIC; 
  signal CHOICE280 : STD_LOGIC; 
  signal CHOICE286 : STD_LOGIC; 
  signal CHOICE291 : STD_LOGIC; 
  signal CHOICE328 : STD_LOGIC; 
  signal CHOICE303 : STD_LOGIC; 
  signal CHOICE327 : STD_LOGIC; 
  signal N10310 : STD_LOGIC; 
  signal N10388 : STD_LOGIC; 
  signal CHOICE228 : STD_LOGIC; 
  signal CHOICE389 : STD_LOGIC; 
  signal CHOICE375 : STD_LOGIC; 
  signal CHOICE372 : STD_LOGIC; 
  signal CHOICE377 : STD_LOGIC; 
  signal CHOICE419 : STD_LOGIC; 
  signal CHOICE468 : STD_LOGIC; 
  signal N10314 : STD_LOGIC; 
  signal CHOICE469 : STD_LOGIC; 
  signal N10396 : STD_LOGIC; 
  signal CHOICE416 : STD_LOGIC; 
  signal CHOICE433 : STD_LOGIC; 
  signal CHOICE466 : STD_LOGIC; 
  signal CHOICE147 : STD_LOGIC; 
  signal CHOICE215 : STD_LOGIC; 
  signal CHOICE217 : STD_LOGIC; 
  signal CHOICE225 : STD_LOGIC; 
  signal N5619 : STD_LOGIC; 
  signal CHOICE131 : STD_LOGIC; 
  signal CHOICE92 : STD_LOGIC; 
  signal N10400 : STD_LOGIC; 
  signal CHOICE35 : STD_LOGIC; 
  signal N10306 : STD_LOGIC; 
  signal N10433 : STD_LOGIC; 
  signal CHOICE17 : STD_LOGIC; 
  signal N10334 : STD_LOGIC; 
  signal N10318 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal a_0_DXMUX : STD_LOGIC; 
  signal a_0_LOGIC_ONE : STD_LOGIC; 
  signal a_0_CYINIT : STD_LOGIC; 
  signal a_0_CYSELF : STD_LOGIC; 
  signal a_N3725 : STD_LOGIC; 
  signal a_0_BXINVNOT : STD_LOGIC; 
  signal a_0_DYMUX : STD_LOGIC; 
  signal a_0_XORG : STD_LOGIC; 
  signal a_0_CYMUXG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_0_cyo : STD_LOGIC; 
  signal a_0_LOGIC_ZERO : STD_LOGIC; 
  signal a_0_CYSELG : STD_LOGIC; 
  signal a_0_G : STD_LOGIC; 
  signal a_0_SRINV : STD_LOGIC; 
  signal a_0_CLKINV : STD_LOGIC; 
  signal a_2_DXMUX : STD_LOGIC; 
  signal a_2_XORF : STD_LOGIC; 
  signal a_2_CYINIT : STD_LOGIC; 
  signal a_2_F : STD_LOGIC; 
  signal a_2_DYMUX : STD_LOGIC; 
  signal a_2_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_2_cyo : STD_LOGIC; 
  signal a_2_CYSELF : STD_LOGIC; 
  signal a_2_CYMUXFAST : STD_LOGIC; 
  signal a_2_CYAND : STD_LOGIC; 
  signal a_2_FASTCARRY : STD_LOGIC; 
  signal a_2_CYMUXG2 : STD_LOGIC; 
  signal a_2_CYMUXF2 : STD_LOGIC; 
  signal a_2_LOGIC_ZERO : STD_LOGIC; 
  signal a_2_CYSELG : STD_LOGIC; 
  signal a_2_G : STD_LOGIC; 
  signal a_2_SRINV : STD_LOGIC; 
  signal a_2_CLKINV : STD_LOGIC; 
  signal a_4_DXMUX : STD_LOGIC; 
  signal a_4_XORF : STD_LOGIC; 
  signal a_4_CYINIT : STD_LOGIC; 
  signal a_4_F : STD_LOGIC; 
  signal a_4_DYMUX : STD_LOGIC; 
  signal a_4_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_4_cyo : STD_LOGIC; 
  signal a_4_CYSELF : STD_LOGIC; 
  signal a_4_CYMUXFAST : STD_LOGIC; 
  signal a_4_CYAND : STD_LOGIC; 
  signal a_4_FASTCARRY : STD_LOGIC; 
  signal a_4_CYMUXG2 : STD_LOGIC; 
  signal a_4_CYMUXF2 : STD_LOGIC; 
  signal a_4_LOGIC_ZERO : STD_LOGIC; 
  signal a_4_CYSELG : STD_LOGIC; 
  signal a_4_G : STD_LOGIC; 
  signal a_4_SRINV : STD_LOGIC; 
  signal a_4_CLKINV : STD_LOGIC; 
  signal a_6_DXMUX : STD_LOGIC; 
  signal a_6_XORF : STD_LOGIC; 
  signal a_6_CYINIT : STD_LOGIC; 
  signal a_6_F : STD_LOGIC; 
  signal a_6_DYMUX : STD_LOGIC; 
  signal a_6_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_6_cyo : STD_LOGIC; 
  signal a_6_CYSELF : STD_LOGIC; 
  signal a_6_CYMUXFAST : STD_LOGIC; 
  signal a_6_CYAND : STD_LOGIC; 
  signal a_6_FASTCARRY : STD_LOGIC; 
  signal a_6_CYMUXG2 : STD_LOGIC; 
  signal a_6_CYMUXF2 : STD_LOGIC; 
  signal a_6_LOGIC_ZERO : STD_LOGIC; 
  signal a_6_CYSELG : STD_LOGIC; 
  signal a_6_G : STD_LOGIC; 
  signal a_6_SRINV : STD_LOGIC; 
  signal a_6_CLKINV : STD_LOGIC; 
  signal a_8_DXMUX : STD_LOGIC; 
  signal a_8_XORF : STD_LOGIC; 
  signal a_8_CYINIT : STD_LOGIC; 
  signal a_8_F : STD_LOGIC; 
  signal a_8_DYMUX : STD_LOGIC; 
  signal a_8_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_8_cyo : STD_LOGIC; 
  signal a_8_CYSELF : STD_LOGIC; 
  signal a_8_CYMUXFAST : STD_LOGIC; 
  signal a_8_CYAND : STD_LOGIC; 
  signal a_8_FASTCARRY : STD_LOGIC; 
  signal a_8_CYMUXG2 : STD_LOGIC; 
  signal a_8_CYMUXF2 : STD_LOGIC; 
  signal a_8_LOGIC_ZERO : STD_LOGIC; 
  signal a_8_CYSELG : STD_LOGIC; 
  signal a_8_G : STD_LOGIC; 
  signal a_8_SRINV : STD_LOGIC; 
  signal a_8_CLKINV : STD_LOGIC; 
  signal a_10_DXMUX : STD_LOGIC; 
  signal a_10_XORF : STD_LOGIC; 
  signal a_10_CYINIT : STD_LOGIC; 
  signal a_10_F : STD_LOGIC; 
  signal a_10_DYMUX : STD_LOGIC; 
  signal a_10_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_10_cyo : STD_LOGIC; 
  signal a_10_CYSELF : STD_LOGIC; 
  signal a_10_CYMUXFAST : STD_LOGIC; 
  signal a_10_CYAND : STD_LOGIC; 
  signal a_10_FASTCARRY : STD_LOGIC; 
  signal a_10_CYMUXG2 : STD_LOGIC; 
  signal a_10_CYMUXF2 : STD_LOGIC; 
  signal a_10_LOGIC_ZERO : STD_LOGIC; 
  signal a_10_CYSELG : STD_LOGIC; 
  signal a_10_G : STD_LOGIC; 
  signal a_10_SRINV : STD_LOGIC; 
  signal a_10_CLKINV : STD_LOGIC; 
  signal a_12_DXMUX : STD_LOGIC; 
  signal a_12_XORF : STD_LOGIC; 
  signal a_12_CYINIT : STD_LOGIC; 
  signal a_12_F : STD_LOGIC; 
  signal a_12_DYMUX : STD_LOGIC; 
  signal a_12_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_12_cyo : STD_LOGIC; 
  signal a_12_CYSELF : STD_LOGIC; 
  signal a_12_CYMUXFAST : STD_LOGIC; 
  signal a_12_CYAND : STD_LOGIC; 
  signal a_12_FASTCARRY : STD_LOGIC; 
  signal a_12_CYMUXG2 : STD_LOGIC; 
  signal a_12_CYMUXF2 : STD_LOGIC; 
  signal a_12_LOGIC_ZERO : STD_LOGIC; 
  signal a_12_CYSELG : STD_LOGIC; 
  signal a_12_G : STD_LOGIC; 
  signal a_12_SRINV : STD_LOGIC; 
  signal a_12_CLKINV : STD_LOGIC; 
  signal a_14_DXMUX : STD_LOGIC; 
  signal a_14_XORF : STD_LOGIC; 
  signal a_14_CYINIT : STD_LOGIC; 
  signal a_14_F : STD_LOGIC; 
  signal a_14_DYMUX : STD_LOGIC; 
  signal a_14_XORG : STD_LOGIC; 
  signal a_LPM_COUNTER_1_n0000_14_cyo : STD_LOGIC; 
  signal a_14_CYSELF : STD_LOGIC; 
  signal a_14_CYMUXFAST : STD_LOGIC; 
  signal a_14_CYAND : STD_LOGIC; 
  signal a_14_FASTCARRY : STD_LOGIC; 
  signal a_14_CYMUXG2 : STD_LOGIC; 
  signal a_14_CYMUXF2 : STD_LOGIC; 
  signal a_14_LOGIC_ZERO : STD_LOGIC; 
  signal a_14_CYSELG : STD_LOGIC; 
  signal a_14_G : STD_LOGIC; 
  signal a_14_SRINV : STD_LOGIC; 
  signal a_14_CLKINV : STD_LOGIC; 
  signal a_16_DXMUX : STD_LOGIC; 
  signal a_16_XORF : STD_LOGIC; 
  signal a_16_CYINIT : STD_LOGIC; 
  signal a_16_F : STD_LOGIC;