szz_map.vhd

来自「VHDL设计的数字时钟」· VHDL 代码 · 共 2,022 行 · 第 1/5 页

  signal sec1_3_SRINV : STD_LOGIC; 
  signal sec1_3_CLKINV : STD_LOGIC; 
  signal sec1_3_CEINV : STD_LOGIC; 
  signal sec2_3_DXMUX : STD_LOGIC; 
  signal sec2_3_DYMUX : STD_LOGIC; 
  signal sec2_3_SRINV : STD_LOGIC; 
  signal sec2_3_CLKINV : STD_LOGIC; 
  signal seth1_3_DXMUX : STD_LOGIC; 
  signal seth1_3_DYMUX : STD_LOGIC; 
  signal seth1_3_SRINV : STD_LOGIC; 
  signal seth1_3_CLKINV : STD_LOGIC; 
  signal seth1_3_CEINV : STD_LOGIC; 
  signal seth2_3_DXMUX : STD_LOGIC; 
  signal seth2_3_DYMUX : STD_LOGIC; 
  signal seth2_3_SRINV : STD_LOGIC; 
  signal seth2_3_CLKINV : STD_LOGIC; 
  signal seth2_3_CEINV : STD_LOGIC; 
  signal setm1_3_DXMUX : STD_LOGIC; 
  signal setm1_3_DYMUX : STD_LOGIC; 
  signal setm1_3_SRINV : STD_LOGIC; 
  signal setm1_3_CLKINV : STD_LOGIC; 
  signal setm1_3_CEINV : STD_LOGIC; 
  signal setm2_3_DXMUX : STD_LOGIC; 
  signal setm2_3_DYMUX : STD_LOGIC; 
  signal setm2_3_SRINV : STD_LOGIC; 
  signal setm2_3_CLKINV : STD_LOGIC; 
  signal setm2_3_CEINV : STD_LOGIC; 
  signal N9038_F : STD_LOGIC; 
  signal N9038_G : STD_LOGIC; 
  signal Q_n0047_F : STD_LOGIC; 
  signal Q_n0047_G : STD_LOGIC; 
  signal s1_2_F : STD_LOGIC; 
  signal s1_2_G : STD_LOGIC; 
  signal CHOICE623_F : STD_LOGIC; 
  signal Q_n0053_7_F : STD_LOGIC; 
  signal Q_n0053_7_G : STD_LOGIC; 
  signal CHOICE502_F : STD_LOGIC; 
  signal CHOICE502_G : STD_LOGIC; 
  signal Q_n0055_F : STD_LOGIC; 
  signal Q_n0055_G : STD_LOGIC; 
  signal CHOICE130_F : STD_LOGIC; 
  signal CHOICE130_G : STD_LOGIC; 
  signal CHOICE513_F : STD_LOGIC; 
  signal Q_n0039_G : STD_LOGIC; 
  signal N10407_F : STD_LOGIC; 
  signal N10407_G : STD_LOGIC; 
  signal Q_n0052_0_F : STD_LOGIC; 
  signal Q_n0052_0_G : STD_LOGIC; 
  signal Q_n0048_F : STD_LOGIC; 
  signal Q_n0048_G : STD_LOGIC; 
  signal CHOICE91_F : STD_LOGIC; 
  signal CHOICE91_G : STD_LOGIC; 
  signal CHOICE119_F : STD_LOGIC; 
  signal CHOICE119_G : STD_LOGIC; 
  signal CHOICE181_F : STD_LOGIC; 
  signal CHOICE181_G : STD_LOGIC; 
  signal CHOICE245_F : STD_LOGIC; 
  signal CHOICE245_G : STD_LOGIC; 
  signal CHOICE630_F : STD_LOGIC; 
  signal CHOICE567_F : STD_LOGIC; 
  signal CHOICE572_F : STD_LOGIC; 
  signal CHOICE644_F : STD_LOGIC; 
  signal Q_n0046_F : STD_LOGIC; 
  signal Q_n0046_G : STD_LOGIC; 
  signal Q_n0044_G : STD_LOGIC; 
  signal CHOICE517_F : STD_LOGIC; 
  signal CHOICE653_F : STD_LOGIC; 
  signal CHOICE532_F : STD_LOGIC; 
  signal CHOICE585_F : STD_LOGIC; 
  signal N10374_F : STD_LOGIC; 
  signal N10374_G : STD_LOGIC; 
  signal CHOICE538_F : STD_LOGIC; 
  signal CHOICE594_F : STD_LOGIC; 
  signal CHOICE544_F : STD_LOGIC; 
  signal CHOICE44_F : STD_LOGIC; 
  signal CHOICE44_G : STD_LOGIC; 
  signal s1_1_F : STD_LOGIC; 
  signal s1_1_G : STD_LOGIC; 
  signal CHOICE128_F : STD_LOGIC; 
  signal CHOICE128_G : STD_LOGIC; 
  signal Q_n0147_F : STD_LOGIC; 
  signal Q_n0147_G : STD_LOGIC; 
  signal N10354_F : STD_LOGIC; 
  signal N10354_G : STD_LOGIC; 
  signal N5812_F : STD_LOGIC; 
  signal m2_1_F : STD_LOGIC; 
  signal m2_1_G : STD_LOGIC; 
  signal s1_0_F : STD_LOGIC; 
  signal s1_0_G : STD_LOGIC; 
  signal CHOICE74_F : STD_LOGIC; 
  signal CHOICE74_G : STD_LOGIC; 
  signal CHOICE212_F : STD_LOGIC; 
  signal CHOICE212_G : STD_LOGIC; 
  signal CHOICE350_F : STD_LOGIC; 
  signal CHOICE350_G : STD_LOGIC; 
  signal m1_0_F : STD_LOGIC; 
  signal m1_0_G : STD_LOGIC; 
  signal N5610_F : STD_LOGIC; 
  signal N5610_G : STD_LOGIC; 
  signal N10424_F : STD_LOGIC; 
  signal N10424_G : STD_LOGIC; 
  signal CHOICE399_F : STD_LOGIC; 
  signal CHOICE399_G : STD_LOGIC; 
  signal N10342_F : STD_LOGIC; 
  signal N10342_G : STD_LOGIC; 
  signal CHOICE668_F : STD_LOGIC; 
  signal CHOICE660_F : STD_LOGIC; 
  signal Q_n0053_6_F : STD_LOGIC; 
  signal Q_n0053_6_G : STD_LOGIC; 
  signal m2_0_F : STD_LOGIC; 
  signal m2_0_G : STD_LOGIC; 
  signal CHOICE232_F : STD_LOGIC; 
  signal CHOICE232_G : STD_LOGIC; 
  signal N10322_F : STD_LOGIC; 
  signal N10322_G : STD_LOGIC; 
  signal CHOICE675_F : STD_LOGIC; 
  signal s2_1_F : STD_LOGIC; 
  signal s2_1_G : STD_LOGIC; 
  signal s2_3_F : STD_LOGIC; 
  signal s2_3_G : STD_LOGIC; 
  signal Q_n0052_2_F : STD_LOGIC; 
  signal Q_n0052_2_G : STD_LOGIC; 
  signal CHOICE28_F : STD_LOGIC; 
  signal CHOICE28_G : STD_LOGIC; 
  signal CHOICE609_F : STD_LOGIC; 
  signal CHOICE601_F : STD_LOGIC; 
  signal CHOICE616_F : STD_LOGIC; 
  signal CHOICE403_F : STD_LOGIC; 
  signal CHOICE403_G : STD_LOGIC; 
  signal CHOICE559_F : STD_LOGIC; 
  signal CHOICE552_F : STD_LOGIC; 
  signal Q_n0053_3_F : STD_LOGIC; 
  signal Q_n0053_3_G : STD_LOGIC; 
  signal CHOICE51_F : STD_LOGIC; 
  signal CHOICE51_G : STD_LOGIC; 
  signal Q_n0053_4_F : STD_LOGIC; 
  signal Q_n0053_4_G : STD_LOGIC; 
  signal CHOICE67_F : STD_LOGIC; 
  signal CHOICE67_G : STD_LOGIC; 
  signal CHOICE59_F : STD_LOGIC; 
  signal CHOICE59_G : STD_LOGIC; 
  signal sec2_1_DXMUX : STD_LOGIC; 
  signal sec2_1_DYMUX : STD_LOGIC; 
  signal sec2_1_G : STD_LOGIC; 
  signal sec2_1_BYINVNOT : STD_LOGIC; 
  signal sec2_1_SRINV : STD_LOGIC; 
  signal sec2_1_CLKINV : STD_LOGIC; 
  signal N10298_F : STD_LOGIC; 
  signal N10298_G : STD_LOGIC; 
  signal sel_0_DXMUX : STD_LOGIC; 
  signal sel_0_F : STD_LOGIC; 
  signal sel_0_BXINVNOT : STD_LOGIC; 
  signal sel_0_DYMUX : STD_LOGIC; 
  signal sel_0_SRINV : STD_LOGIC; 
  signal sel_0_CLKINV : STD_LOGIC; 
  signal CHOICE280_F : STD_LOGIC; 
  signal CHOICE280_G : STD_LOGIC; 
  signal CHOICE286_F : STD_LOGIC; 
  signal CHOICE286_G : STD_LOGIC; 
  signal speak_N402_F : STD_LOGIC; 
  signal speak_N402_G : STD_LOGIC; 
  signal CHOICE303_F : STD_LOGIC; 
  signal CHOICE303_G : STD_LOGIC; 
  signal hou1_0_DXMUX : STD_LOGIC; 
  signal hou1_0_BXINVNOT : STD_LOGIC; 
  signal hou1_0_DYMUX : STD_LOGIC; 
  signal hou1_0_SRINV : STD_LOGIC; 
  signal hou1_0_CLKINV : STD_LOGIC; 
  signal hou1_0_CEINV : STD_LOGIC; 
  signal hou2_0_DXMUX : STD_LOGIC; 
  signal hou2_0_BXINVNOT : STD_LOGIC; 
  signal hou2_0_DYMUX : STD_LOGIC; 
  signal hou2_0_SRINV : STD_LOGIC; 
  signal hou2_0_CLKINV : STD_LOGIC; 
  signal hou2_0_CEINV : STD_LOGIC; 
  signal min1_0_DXMUX : STD_LOGIC; 
  signal min1_0_BXINVNOT : STD_LOGIC; 
  signal min1_0_DYMUX : STD_LOGIC; 
  signal min1_0_SRINV : STD_LOGIC; 
  signal min1_0_CLKINV : STD_LOGIC; 
  signal min1_0_CEINV : STD_LOGIC; 
  signal min2_0_DXMUX : STD_LOGIC; 
  signal min2_0_BXINVNOT : STD_LOGIC; 
  signal min2_0_DYMUX : STD_LOGIC; 
  signal min2_0_SRINV : STD_LOGIC; 
  signal min2_0_CLKINV : STD_LOGIC; 
  signal min2_0_CEINV : STD_LOGIC; 
  signal N10388_F : STD_LOGIC; 
  signal N10388_G : STD_LOGIC; 
  signal CHOICE228_F : STD_LOGIC; 
  signal CHOICE228_G : STD_LOGIC; 
  signal CHOICE389_F : STD_LOGIC; 
  signal CHOICE389_G : STD_LOGIC; 
  signal CHOICE377_F : STD_LOGIC; 
  signal CHOICE377_G : STD_LOGIC; 
  signal CHOICE469_F : STD_LOGIC; 
  signal CHOICE469_G : STD_LOGIC; 
  signal N10396_F : STD_LOGIC; 
  signal N10396_G : STD_LOGIC; 
  signal sec1_0_DXMUX : STD_LOGIC; 
  signal sec1_0_BXINVNOT : STD_LOGIC; 
  signal sec1_0_DYMUX : STD_LOGIC; 
  signal sec1_0_SRINV : STD_LOGIC; 
  signal sec1_0_CLKINV : STD_LOGIC; 
  signal sec1_0_CEINV : STD_LOGIC; 
  signal N10314_F : STD_LOGIC; 
  signal N10314_G : STD_LOGIC; 
  signal CHOICE468_F : STD_LOGIC; 
  signal CHOICE468_G : STD_LOGIC; 
  signal CHOICE147_F : STD_LOGIC; 
  signal CHOICE147_G : STD_LOGIC; 
  signal CHOICE217_F : STD_LOGIC; 
  signal CHOICE217_G : STD_LOGIC; 
  signal clk1_DYMUX : STD_LOGIC; 
  signal clk1_BYINVNOT : STD_LOGIC; 
  signal clk1_CLKINV : STD_LOGIC; 
  signal clk1_CEINV : STD_LOGIC; 
  signal clk2_DYMUX : STD_LOGIC; 
  signal clk2_BYINVNOT : STD_LOGIC; 
  signal clk2_CLKINV : STD_LOGIC; 
  signal clk2_CEINV : STD_LOGIC; 
  signal CHOICE22_F : STD_LOGIC; 
  signal CHOICE22_G : STD_LOGIC; 
  signal Q_n0035_G : STD_LOGIC; 
  signal CHOICE225_F : STD_LOGIC; 
  signal Q_n0053_2_F : STD_LOGIC; 
  signal Q_n0053_2_G : STD_LOGIC; 
  signal CHOICE93_F : STD_LOGIC; 
  signal CHOICE93_G : STD_LOGIC; 
  signal CHOICE372_F : STD_LOGIC; 
  signal CHOICE372_G : STD_LOGIC; 
  signal seth1_0_DXMUX : STD_LOGIC; 
  signal seth1_0_BXINVNOT : STD_LOGIC; 
  signal seth1_0_DYMUX : STD_LOGIC; 
  signal seth1_0_SRINV : STD_LOGIC; 
  signal seth1_0_CLKINV : STD_LOGIC; 
  signal seth1_0_CEINV : STD_LOGIC; 
  signal seth2_0_DXMUX : STD_LOGIC; 
  signal seth2_0_BXINVNOT : STD_LOGIC; 
  signal seth2_0_DYMUX : STD_LOGIC; 
  signal seth2_0_SRINV : STD_LOGIC; 
  signal seth2_0_CLKINV : STD_LOGIC; 
  signal seth2_0_CEINV : STD_LOGIC; 
  signal CHOICE36_F : STD_LOGIC; 
  signal CHOICE36_G : STD_LOGIC; 
  signal setm1_0_DXMUX : STD_LOGIC; 
  signal setm1_0_BXINVNOT : STD_LOGIC; 
  signal setm1_0_DYMUX : STD_LOGIC; 
  signal setm1_0_SRINV : STD_LOGIC; 
  signal setm1_0_CLKINV : STD_LOGIC; 
  signal setm1_0_CEINV : STD_LOGIC; 
  signal setm2_0_DXMUX : STD_LOGIC; 
  signal setm2_0_BXINVNOT : STD_LOGIC; 
  signal setm2_0_DYMUX : STD_LOGIC; 
  signal setm2_0_SRINV : STD_LOGIC; 
  signal setm2_0_CLKINV : STD_LOGIC; 
  signal setm2_0_CEINV : STD_LOGIC; 
  signal CHOICE327_F : STD_LOGIC; 
  signal CHOICE327_G : STD_LOGIC; 
  signal clk_DYMUX : STD_LOGIC; 
  signal clk_BYINVNOT : STD_LOGIC; 
  signal clk_CLKINV : STD_LOGIC; 
  signal clk_CEINV : STD_LOGIC; 
  signal CHOICE466_F : STD_LOGIC; 
  signal CHOICE466_G : STD_LOGIC; 
  signal N5619_F : STD_LOGIC; 
  signal N5619_G : STD_LOGIC; 
  signal Q_n0053_1_F : STD_LOGIC; 
  signal Q_n0053_1_G : STD_LOGIC; 
  signal Q_n0053_5_F : STD_LOGIC; 
  signal Q_n0053_5_G : STD_LOGIC; 
  signal dout_2 : STD_LOGIC; 
  signal dout_2_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal dout_2_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal dout_3_OUTPUT_OTCLK1INVNOT : STD_LOGIC; 
  signal dout_3 : STD_LOGIC; 
  signal dout_3_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal dout_3_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal dout_4_OUTPUT_OTCLK1INVNOT : STD_LOGIC; 
  signal dout_4 : STD_LOGIC; 
  signal dout_4_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal dout_4_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal dout_5_OUTPUT_OTCLK1INVNOT : STD_LOGIC; 
  signal dout_5 : STD_LOGIC; 
  signal dout_5_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal dout_5_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal dout_1 : STD_LOGIC; 
  signal dout_1_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal dout_1_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal dout_6 : STD_LOGIC; 
  signal dout_6_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal dout_6_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal dout_7_OUTPUT_OTCLK1INVNOT : STD_LOGIC; 
  signal dout_7 : STD_LOGIC; 
  signal dout_7_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal dout_7_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal speak_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal speak_OBUF : STD_LOGIC; 
  signal speak_OUTPUT_OFF_OSR_USED : STD_LOGIC; 
  signal speak_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal dout_0_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal dout_0_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal dout_0 : STD_LOGIC; 
  signal dout_0_OUTPUT_OTCLK1INVNOT : STD_LOGIC; 
  signal selout_0 : STD_LOGIC; 
  signal selout_0_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal selout_0_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal selout_1_OUTPUT_OTCLK1INVNOT : STD_LOGIC; 
  signal selout_1 : STD_LOGIC; 
  signal selout_1_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal selout_1_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal selout_2_OUTPUT_OTCLK1INVNOT : STD_LOGIC; 
  signal selout_2 : STD_LOGIC; 
  signal selout_2_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal selout_2_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal selout_3_OUTPUT_OTCLK1INVNOT : STD_LOGIC; 
  signal selout_3 : STD_LOGIC; 
  signal selout_3_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal selout_3_OUTPUT_OFF_OFF1_RST : STD_LOGIC; 
  signal clk1_FFY_RST : STD_LOGIC; 
  signal clk2_FFY_RST : STD_LOGIC; 
  signal clk_FFY_RST : STD_LOGIC; 
  signal CE_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NlwInverterSignal_dout_2_CLK : STD_LOGIC; 
  signal NlwInverterSignal_dout_3_CLK : STD_LOGIC; 
  signal NlwInverterSignal_dout_4_CLK : STD_LOGIC; 
  signal NlwInverterSignal_dout_5_CLK : STD_LOGIC; 
  signal NlwInverterSignal_dout_1_CLK : STD_LOGIC; 
  signal NlwInverterSignal_dout_6_CLK : STD_LOGIC; 
  signal NlwInverterSignal_dout_7_CLK : STD_LOGIC; 
  signal NlwInverterSignal_dout_0_CLK : STD_LOGIC; 
  signal NlwInverterSignal_selout_0_CLK : STD_LOGIC; 
  signal NlwInverterSignal_selout_1_CLK : STD_LOGIC; 
  signal NlwInverterSignal_selout_2_CLK : STD_LOGIC; 
  signal NlwInverterSignal_selout_3_CLK : STD_LOGIC; 
  signal a : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal b : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal c : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal Q_n0053 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Q_n0052 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal s2 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal h2 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal s1 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal hou1 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal seth1 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal h1 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal sec2 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal min1 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal hou2 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal min2 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal sec1 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal sel : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal seth2 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal setm1 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal setm2 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal m1 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal m2 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal sel_n0000 : STD_LOGIC_VECTOR ( 2 downto 1 ); 
  signal hou1_n0000 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal hou2_n0000 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal min1_n0000 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal min2_n0000 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal sec1_n0000 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal sec2_n0000 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal seth1_n0000 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal seth2_n0000 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal setm1_n0000 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal setm2_n0000 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
begin
  GLOBAL_LOGIC0_ZERO : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  GLOBAL_LOGIC1_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  a_0_LOGIC_ZERO_0 : X_ZERO
    port map (
      O => a_0_LOGIC_ZERO
    );
  a_0_LOGIC_ONE_1 : X_ONE
    port map (
      O => a_0_LOGIC_ONE
    );
  a_0_DXMUX_2 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_N3725,
      O => a_0_DXMUX
    );
  a_0_CYMUXF : X_MUX2
    port map (
      IA => a_0_LOGIC_ONE,
      IB => a_0_CYINIT,
      SEL => a_0_CYSELF,
      O => a_LPM_COUNTER_1_n0000_0_cyo
    );
  a_0_CYINIT_3 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps