traffic.tan.rpt

verilog HDL综合实验源代码

; N/A   ; None         ; 18.000 ns  ; first[0]   ; dataout[3] ; clk        ;
; N/A   ; None         ; 18.000 ns  ; first[2]   ; dataout[3] ; clk        ;
; N/A   ; None         ; 18.000 ns  ; en[0]~reg0 ; dataout[1] ; clk        ;
; N/A   ; None         ; 18.000 ns  ; en[1]~reg0 ; dataout[1] ; clk        ;
; N/A   ; None         ; 18.000 ns  ; first[3]   ; dataout[1] ; clk        ;
; N/A   ; None         ; 18.000 ns  ; first[1]   ; dataout[1] ; clk        ;
; N/A   ; None         ; 18.000 ns  ; first[0]   ; dataout[1] ; clk        ;
; N/A   ; None         ; 18.000 ns  ; first[2]   ; dataout[1] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; en[0]~reg0 ; dataout[5] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; en[1]~reg0 ; dataout[5] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; first[3]   ; dataout[5] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; first[1]   ; dataout[5] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; first[0]   ; dataout[5] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; first[2]   ; dataout[5] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; second[2]  ; dataout[5] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; second[0]  ; dataout[5] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; second[1]  ; dataout[5] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; second[2]  ; dataout[3] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; second[0]  ; dataout[3] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; second[1]  ; dataout[3] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; second[2]  ; dataout[1] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; second[0]  ; dataout[1] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; second[1]  ; dataout[1] ; clk        ;
; N/A   ; None         ; 17.000 ns  ; state~48   ; light[2]   ; clk        ;
; N/A   ; None         ; 17.000 ns  ; state~47   ; light[2]   ; clk        ;
; N/A   ; None         ; 17.000 ns  ; state~47   ; light[1]   ; clk        ;
; N/A   ; None         ; 17.000 ns  ; state~48   ; light[0]   ; clk        ;
; N/A   ; None         ; 8.000 ns   ; en[1]~reg0 ; en[1]      ; clk        ;
; N/A   ; None         ; 8.000 ns   ; en[0]~reg0 ; en[0]      ; clk        ;
+-------+--------------+------------+------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 14 14:42:57 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off traffic -c traffic
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 47.62 MHz between source register "cnt[19]" and destination register "cnt[9]" (period= 21.0 ns)
    Info: + Longest register to register delay is 16.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC106; Fanout = 30; REG Node = 'cnt[19]'
        Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP1; Fanout = 3; COMB Node = 'reduce_or~2415sexp'
        Info: 3: + IC(0.000 ns) + CELL(6.000 ns) = 16.000 ns; Loc. = LC9; Fanout = 40; REG Node = 'cnt[9]'
        Info: Total cell delay = 14.000 ns ( 87.50 % )
        Info: Total interconnect delay = 2.000 ns ( 12.50 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 53; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC9; Fanout = 40; REG Node = 'cnt[9]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 53; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC106; Fanout = 30; REG Node = 'cnt[19]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock "clk" to destination pin "dataout[2]" through register "en[0]~reg0" is 27.000 ns
    Info: + Longest clock path from clock "clk" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 53; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC118; Fanout = 42; REG Node = 'en[0]~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 23.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC118; Fanout = 42; REG Node = 'en[0]~reg0'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC81; Fanout = 1; COMB Node = 'reduce_or~2485'
        Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 10.000 ns; Loc. = LC82; Fanout = 1; COMB Node = 'reduce_or~2433'
        Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC86; Fanout = 1; COMB Node = 'reduce_or~2490'
        Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 23.000 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'dataout[2]'
        Info: Total cell delay = 19.000 ns ( 82.61 % )
        Info: Total interconnect delay = 4.000 ns ( 17.39 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Dec 14 14:42:58 2005
    Info: Elapsed time: 00:00:02