frequency_counter_2.sim.qmsg

这是关于VHDL模块的源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 11 22:26:04 2005 " "Info: Processing started: Tue Oct 11 22:26:04 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off frequency_counter_2 -c frequency_counter_2 " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off frequency_counter_2 -c frequency_counter_2" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|frequency_counter_2\|reg_32bit:u_reg_32bit\|dout\[0\] 300.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 300.0 ns on register \"\|frequency_counter_2\|reg_32bit:u_reg_32bit\|dout\[0\]\"" {  } {  } 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "      7.83 % " "Info: Simulation coverage is       7.83 %" {  } {  } 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "429 " "Info: Number of transitions in simulation is 429" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 1  Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 11 22:26:05 2005 " "Info: Processing ended: Tue Oct 11 22:26:05 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}